JPS5748149A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5748149A
JPS5748149A JP55122734A JP12273480A JPS5748149A JP S5748149 A JPS5748149 A JP S5748149A JP 55122734 A JP55122734 A JP 55122734A JP 12273480 A JP12273480 A JP 12273480A JP S5748149 A JPS5748149 A JP S5748149A
Authority
JP
Japan
Prior art keywords
connecting line
data width
bytes
data
longer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55122734A
Other languages
Japanese (ja)
Inventor
Naoteru Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55122734A priority Critical patent/JPS5748149A/en
Publication of JPS5748149A publication Critical patent/JPS5748149A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To attain an access operation, by using the memory data width which is longer than one word length of a computer by use of plural split memory circuits, and making the time required for partial write almost same as that of full write. CONSTITUTION:Address information provided to an address register 1 through a connecting line 11 is provided to split memory circuits 100, 200 through a connecting line 12. Also, a split memory circuit gate signal is sent to the split memory circuits 100, 200 through a connecting line 10. The memory circuit 100 and 200 have data width of (m) bytes, respectively, and in case a data of 2m bytes is written, data of each (m) bytes are sent to the memory circuit 100 and 200 through a connecting line 113 and 213, and are read out through a connecting line 120 and 220. In this way, even if the data width being longer than one word length of a computer is used, the time required for partial write and full write can be made same even if the data width which is longer than one word length of a computer is used.
JP55122734A 1980-09-04 1980-09-04 Memory device Pending JPS5748149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55122734A JPS5748149A (en) 1980-09-04 1980-09-04 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55122734A JPS5748149A (en) 1980-09-04 1980-09-04 Memory device

Publications (1)

Publication Number Publication Date
JPS5748149A true JPS5748149A (en) 1982-03-19

Family

ID=14843260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55122734A Pending JPS5748149A (en) 1980-09-04 1980-09-04 Memory device

Country Status (1)

Country Link
JP (1) JPS5748149A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155755A (en) * 1984-08-27 1986-03-20 Mitsubishi Electric Corp Memory control device
JPH02159649A (en) * 1988-12-13 1990-06-19 Hitachi Ltd Storage circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155755A (en) * 1984-08-27 1986-03-20 Mitsubishi Electric Corp Memory control device
JPH02159649A (en) * 1988-12-13 1990-06-19 Hitachi Ltd Storage circuit

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