JPS56156978A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS56156978A
JPS56156978A JP5751980A JP5751980A JPS56156978A JP S56156978 A JPS56156978 A JP S56156978A JP 5751980 A JP5751980 A JP 5751980A JP 5751980 A JP5751980 A JP 5751980A JP S56156978 A JPS56156978 A JP S56156978A
Authority
JP
Japan
Prior art keywords
addresses
read
registers
bits
order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5751980A
Other languages
Japanese (ja)
Inventor
Yasuyuki Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5751980A priority Critical patent/JPS56156978A/en
Publication of JPS56156978A publication Critical patent/JPS56156978A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To reduce the read times of a main memory with simple constitution by storing the read information from the plural address areas of the main memory into data registers and selectively outputting the same. CONSTITUTION:The information in the areas corresponding to the addresses excluding the low-order 2 bits of the memory blocks MB0... of a main memory 102 is read out through a control circuit 108 to which the read command signal according to the addresses from a CPU101 and are stored in data registers 1051, 1052.... According to the low-order 2 bits of the addresses, the registers 1051... are selected by a data selector 107, and the read information is sent to the CPU101. At the same time, an FF106 forming flags is set and the addresses are latched in an address register 103. They are compared with the read addresses excluding the next low- order 2 bits in the circuit 108 and when they coincide, no rereading of the memory 102 is accomplished and the registers 1051... are selected.
JP5751980A 1980-04-30 1980-04-30 Memory control system Pending JPS56156978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5751980A JPS56156978A (en) 1980-04-30 1980-04-30 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5751980A JPS56156978A (en) 1980-04-30 1980-04-30 Memory control system

Publications (1)

Publication Number Publication Date
JPS56156978A true JPS56156978A (en) 1981-12-03

Family

ID=13057977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5751980A Pending JPS56156978A (en) 1980-04-30 1980-04-30 Memory control system

Country Status (1)

Country Link
JP (1) JPS56156978A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59500836A (en) * 1982-05-10 1984-05-10 エヌ・シ−・ア−ル・コ−ポレ−シヨン memory addressing system
JPS63271647A (en) * 1987-04-30 1988-11-09 Yokogawa Medical Syst Ltd Memory circuit
JPS6488760A (en) * 1987-09-30 1989-04-03 Toshiba Corp Memory data fetching system
WO1992005489A1 (en) * 1990-09-18 1992-04-02 Fujitsu Limited Method of nonsynchronous access to shared memory
JPH0466649U (en) * 1990-10-11 1992-06-12
US6108755A (en) * 1990-09-18 2000-08-22 Fujitsu Limited Asynchronous access system to a shared storage

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59500836A (en) * 1982-05-10 1984-05-10 エヌ・シ−・ア−ル・コ−ポレ−シヨン memory addressing system
JPS63271647A (en) * 1987-04-30 1988-11-09 Yokogawa Medical Syst Ltd Memory circuit
JPS6488760A (en) * 1987-09-30 1989-04-03 Toshiba Corp Memory data fetching system
WO1992005489A1 (en) * 1990-09-18 1992-04-02 Fujitsu Limited Method of nonsynchronous access to shared memory
US6108755A (en) * 1990-09-18 2000-08-22 Fujitsu Limited Asynchronous access system to a shared storage
JP3141948B2 (en) * 1990-09-18 2001-03-07 富士通株式会社 Computer system
JPH0466649U (en) * 1990-10-11 1992-06-12

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