JPS5616980A - Write-in system of one-bit of memory - Google Patents

Write-in system of one-bit of memory

Info

Publication number
JPS5616980A
JPS5616980A JP9226779A JP9226779A JPS5616980A JP S5616980 A JPS5616980 A JP S5616980A JP 9226779 A JP9226779 A JP 9226779A JP 9226779 A JP9226779 A JP 9226779A JP S5616980 A JPS5616980 A JP S5616980A
Authority
JP
Japan
Prior art keywords
bit
memory
address
write
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9226779A
Other languages
Japanese (ja)
Other versions
JPS5712219B2 (en
Inventor
Akito Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9226779A priority Critical patent/JPS5616980A/en
Publication of JPS5616980A publication Critical patent/JPS5616980A/en
Publication of JPS5712219B2 publication Critical patent/JPS5712219B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To enable the write-in in one bit, cancell the processing required for edit of memory data, and to make efficient the data processing, by setting the desired address to the register indicating an arbitrary bit-address in word. CONSTITUTION:The bit wirte-in mode is provided, the memory address written in one bit is set to the address registers 4, 4', and the address is read out and set to the readout register 3. When the data from the memory 1 is set to the register 3, the write-in pulse signal is produced from the memory control section 1', the bit address given in advance and the one bit write-in data are written in the bit location of the memory 1 designated with the bit selection address decoder 5, and in other bits, the content of the register 3 is written in the memory 1 as it is. Thus, the one- bit write-in to the memory 1 is made.
JP9226779A 1979-07-20 1979-07-20 Write-in system of one-bit of memory Granted JPS5616980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9226779A JPS5616980A (en) 1979-07-20 1979-07-20 Write-in system of one-bit of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9226779A JPS5616980A (en) 1979-07-20 1979-07-20 Write-in system of one-bit of memory

Publications (2)

Publication Number Publication Date
JPS5616980A true JPS5616980A (en) 1981-02-18
JPS5712219B2 JPS5712219B2 (en) 1982-03-09

Family

ID=14049615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9226779A Granted JPS5616980A (en) 1979-07-20 1979-07-20 Write-in system of one-bit of memory

Country Status (1)

Country Link
JP (1) JPS5616980A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6194143A (en) * 1984-10-15 1986-05-13 Matsushita Electric Ind Co Ltd Data transfer device
JPS61236247A (en) * 1985-04-12 1986-10-21 Hitachi Ltd Method for coping with network disturbance
JPS62217483A (en) * 1986-03-17 1987-09-24 Mitsubishi Electric Corp Memory device
JPS6352244A (en) * 1986-08-21 1988-03-05 Ascii Corp Memory device
JPS63192170A (en) * 1987-02-05 1988-08-09 Furuno Electric Co Ltd Picture memory circuit
JPH0191547A (en) * 1987-06-09 1989-04-11 Fujitsu Ltd Common bus system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6194143A (en) * 1984-10-15 1986-05-13 Matsushita Electric Ind Co Ltd Data transfer device
JPS61236247A (en) * 1985-04-12 1986-10-21 Hitachi Ltd Method for coping with network disturbance
JPS62217483A (en) * 1986-03-17 1987-09-24 Mitsubishi Electric Corp Memory device
JPS6352244A (en) * 1986-08-21 1988-03-05 Ascii Corp Memory device
JPS63192170A (en) * 1987-02-05 1988-08-09 Furuno Electric Co Ltd Picture memory circuit
JPH0191547A (en) * 1987-06-09 1989-04-11 Fujitsu Ltd Common bus system

Also Published As

Publication number Publication date
JPS5712219B2 (en) 1982-03-09

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