JPS5719856A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5719856A
JPS5719856A JP9253780A JP9253780A JPS5719856A JP S5719856 A JPS5719856 A JP S5719856A JP 9253780 A JP9253780 A JP 9253780A JP 9253780 A JP9253780 A JP 9253780A JP S5719856 A JPS5719856 A JP S5719856A
Authority
JP
Japan
Prior art keywords
address
memory
signal
data
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9253780A
Other languages
Japanese (ja)
Inventor
Masanobu Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9253780A priority Critical patent/JPS5719856A/en
Publication of JPS5719856A publication Critical patent/JPS5719856A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To increase a memory capacity without extending an address, and also to easily handle a data having length of >=(two words), by assigning a data of >=(two words) to one address of a memory. CONSTITUTION:When (n) address is designated to an address signal 11 and a write signal 13 is outputted, a data signal 14 is sent to a memory 4.1 through an input control part 6, and is written in n-th memory by a memory driving circuit 3. In a state that the (n) address has been latched by a register 2, when a+1 address is designated to the signal 11 and the signal 13 is outputted, the signal 14 is written in the (n) address of the memory 4.1+1. Accordingly, when a+1 address is made (a) address, a+1 address...a+m-1 address, a data can be written in 1st, 2nd... m-th depth of (n) address.
JP9253780A 1980-07-07 1980-07-07 Memory control system Pending JPS5719856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9253780A JPS5719856A (en) 1980-07-07 1980-07-07 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9253780A JPS5719856A (en) 1980-07-07 1980-07-07 Memory control system

Publications (1)

Publication Number Publication Date
JPS5719856A true JPS5719856A (en) 1982-02-02

Family

ID=14057111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9253780A Pending JPS5719856A (en) 1980-07-07 1980-07-07 Memory control system

Country Status (1)

Country Link
JP (1) JPS5719856A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59157882A (en) * 1983-02-28 1984-09-07 Nec Home Electronics Ltd Memory circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59157882A (en) * 1983-02-28 1984-09-07 Nec Home Electronics Ltd Memory circuit

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