JPS56155464A - Computer connector - Google Patents

Computer connector

Info

Publication number
JPS56155464A
JPS56155464A JP5905480A JP5905480A JPS56155464A JP S56155464 A JPS56155464 A JP S56155464A JP 5905480 A JP5905480 A JP 5905480A JP 5905480 A JP5905480 A JP 5905480A JP S56155464 A JPS56155464 A JP S56155464A
Authority
JP
Japan
Prior art keywords
data
input
main memory
output controller
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5905480A
Other languages
Japanese (ja)
Other versions
JPS6126706B2 (en
Inventor
Katsumi Muraki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5905480A priority Critical patent/JPS56155464A/en
Publication of JPS56155464A publication Critical patent/JPS56155464A/en
Publication of JPS6126706B2 publication Critical patent/JPS6126706B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To make data transfer possible even when the program of the other computer is destructed, by providing an input/output controller which writes information of the main memory of one computer to the memory of the other computer directly. CONSTITUTION:CPU103 transmits the data address of main memory 101, the data address of main memory 311 of the transmission destination, and data to input/output controller 58 through signal line 105. Input/output controller 58 stores these data addresses and data in address register 52 and data register 53, respectively and transmits the data address of main memory 311 and data to input/output controller 68 through data bus 72. Input/output controller 68 receives this signal to store them in its own address register 62 and data register 63 without reporting it to CPU312. As a result, data is transferred to main memory 311 directly independently of CPU312.
JP5905480A 1980-05-02 1980-05-02 Computer connector Granted JPS56155464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5905480A JPS56155464A (en) 1980-05-02 1980-05-02 Computer connector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5905480A JPS56155464A (en) 1980-05-02 1980-05-02 Computer connector

Publications (2)

Publication Number Publication Date
JPS56155464A true JPS56155464A (en) 1981-12-01
JPS6126706B2 JPS6126706B2 (en) 1986-06-21

Family

ID=13102222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5905480A Granted JPS56155464A (en) 1980-05-02 1980-05-02 Computer connector

Country Status (1)

Country Link
JP (1) JPS56155464A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0095363A2 (en) * 1982-05-21 1983-11-30 Pitney Bowes, Inc. Direct memory access data transfer system for use with plural processors
JPS59141229U (en) * 1983-03-12 1984-09-20 株式会社クボタ Rotation synchronized transmission
JPS62152057A (en) * 1985-12-26 1987-07-07 Nec Corp Data transfer device
JPS6433656A (en) * 1987-07-30 1989-02-03 Nec Corp Control system for transfer of data
JP2004508635A (en) * 2000-09-06 2004-03-18 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Communication system between processors

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0095363A2 (en) * 1982-05-21 1983-11-30 Pitney Bowes, Inc. Direct memory access data transfer system for use with plural processors
JPS59141229U (en) * 1983-03-12 1984-09-20 株式会社クボタ Rotation synchronized transmission
JPS62152057A (en) * 1985-12-26 1987-07-07 Nec Corp Data transfer device
JPS6433656A (en) * 1987-07-30 1989-02-03 Nec Corp Control system for transfer of data
JP2004508635A (en) * 2000-09-06 2004-03-18 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Communication system between processors
JP4915631B2 (en) * 2000-09-06 2012-04-11 エスティー‐エリクソン、ソシエテ、アノニム Interprocessor communication system

Also Published As

Publication number Publication date
JPS6126706B2 (en) 1986-06-21

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