JPS56155463A - Data transferring system - Google Patents

Data transferring system

Info

Publication number
JPS56155463A
JPS56155463A JP5832680A JP5832680A JPS56155463A JP S56155463 A JPS56155463 A JP S56155463A JP 5832680 A JP5832680 A JP 5832680A JP 5832680 A JP5832680 A JP 5832680A JP S56155463 A JPS56155463 A JP S56155463A
Authority
JP
Japan
Prior art keywords
line
address
data
generated
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5832680A
Other languages
Japanese (ja)
Inventor
Kenichi Onishi
Minoru Nagao
Makoto Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP5832680A priority Critical patent/JPS56155463A/en
Publication of JPS56155463A publication Critical patent/JPS56155463A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To simplify the program of the master CPU, by designating addresses concerning data transfer by the slave CPU. CONSTITUTION:Master CPU20 disconnects address bus 30, data bus 40 and line 50 electrically from one another to output data transfer permission signal H to line 70 when slave CPU120 is permitted to access main storage device 10 after master CPU20 receives the data transfer request signal through line 60. When permission signal H is outputted, all input terminals of AND circuit 104 become high-level, and the high-level signal is outputted to line 105 to open gates of buffers 181, 182, and 183. Consequently, the address code is generated on address bus 30 through address busses 131 and 31, and data is generated on data bus 40 through busses 141 and 41, and the writing signal is generated on line 50 through lines 152 and 51, and thus, data is written in the address of main storage device 10.
JP5832680A 1980-04-30 1980-04-30 Data transferring system Pending JPS56155463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5832680A JPS56155463A (en) 1980-04-30 1980-04-30 Data transferring system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5832680A JPS56155463A (en) 1980-04-30 1980-04-30 Data transferring system

Publications (1)

Publication Number Publication Date
JPS56155463A true JPS56155463A (en) 1981-12-01

Family

ID=13081166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5832680A Pending JPS56155463A (en) 1980-04-30 1980-04-30 Data transferring system

Country Status (1)

Country Link
JP (1) JPS56155463A (en)

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