JPS5687149A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS5687149A
JPS5687149A JP16502479A JP16502479A JPS5687149A JP S5687149 A JPS5687149 A JP S5687149A JP 16502479 A JP16502479 A JP 16502479A JP 16502479 A JP16502479 A JP 16502479A JP S5687149 A JPS5687149 A JP S5687149A
Authority
JP
Japan
Prior art keywords
memory
input
output devices
bus
transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16502479A
Other languages
Japanese (ja)
Inventor
Osamu Araya
Haruki Matsui
Makoto Tateishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16502479A priority Critical patent/JPS5687149A/en
Publication of JPS5687149A publication Critical patent/JPS5687149A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To enable the transfer of effective information, by using the time difference of access time of a memory and a CPU, while switching an address bus, data bus and control bus which are used in common.
CONSTITUTION: Among CPU1, direct memory access device 2 and input and output devices 4W7, the address bus AB, data bus DB, and control bus CB are connected and the transfer of information is made among the memory 3 and the input and output devices 4W7, then the device 2 from CPU1 and the memory 3 via the buses CB, AB and DB, are set with the start address and transfer number of information. Further, connection is made so that the direct memory access DMA can be made to the input and output devices 4W7, and the input and output devices 4W7 connected supply the DMA request to the device 2. Next, the device 2 receives the request and feeds the approval signal to the input and output devices 4W7, the start address of the memory 3 is output to the bus AB, utilizing the time difference of the access time of CPU and memory, allow to transfer the information effectively.
COPYRIGHT: (C)1981,JPO&Japio
JP16502479A 1979-12-19 1979-12-19 Memory access control system Pending JPS5687149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16502479A JPS5687149A (en) 1979-12-19 1979-12-19 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16502479A JPS5687149A (en) 1979-12-19 1979-12-19 Memory access control system

Publications (1)

Publication Number Publication Date
JPS5687149A true JPS5687149A (en) 1981-07-15

Family

ID=15804389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16502479A Pending JPS5687149A (en) 1979-12-19 1979-12-19 Memory access control system

Country Status (1)

Country Link
JP (1) JPS5687149A (en)

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