JPS54146555A - Data transfer system between processors - Google Patents

Data transfer system between processors

Info

Publication number
JPS54146555A
JPS54146555A JP5520478A JP5520478A JPS54146555A JP S54146555 A JPS54146555 A JP S54146555A JP 5520478 A JP5520478 A JP 5520478A JP 5520478 A JP5520478 A JP 5520478A JP S54146555 A JPS54146555 A JP S54146555A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
command
writing
given
reading
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5520478A
Other versions
JPS6124738B2 (en )
Inventor
Kazuo Takagaki
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To enable an immediate data transfer process for the reading command after the end of the data transfer process of the writing command by giving previously the reading command to the 3rd processor.
CONSTITUTION: The 3rd processor existing between the 1st and 2nd processors comprises transfer circuit 10 which shares the data transfer for both processors, transfer circuit 11 which transfers the data in the opposite direction, and command distribution circuit 12 which distributes the commands given from the 1st and 2nd processors to circuit 10 and 11. In case the writing command is given after the reading command, the reading command from circuit 12 is stored in reading command register 115. Then the writing is given to buffer 111 when the writing command is stored into writing command register 114 via circuit 12. The reading is carried out from buffer 111 when the writing is over. In case the reading command is given after the writing order, the command is stored into register 114 and then the writing is given to buffer 111 to be then read out by the reading command given to register 115.
COPYRIGHT: (C)1979,JPO&Japio
JP5520478A 1978-05-09 1978-05-09 Expired JPS6124738B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5520478A JPS6124738B2 (en) 1978-05-09 1978-05-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5520478A JPS6124738B2 (en) 1978-05-09 1978-05-09

Publications (2)

Publication Number Publication Date
JPS54146555A true true JPS54146555A (en) 1979-11-15
JPS6124738B2 JPS6124738B2 (en) 1986-06-12

Family

ID=12992128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5520478A Expired JPS6124738B2 (en) 1978-05-09 1978-05-09

Country Status (1)

Country Link
JP (1) JPS6124738B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002077838A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Resource dedication system and method for a computer architecture for broadband networks
WO2002077845A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
WO2002077848A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
WO2002077846A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. System and method for data synchronization for a computer architecture for broadband networks
US7024519B2 (en) 2002-05-06 2006-04-04 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
JP2006107514A (en) * 2004-10-05 2006-04-20 Sony Computer Entertainment Inc System and device which have interface device which can perform data communication with external device
US7139882B2 (en) 2001-03-22 2006-11-21 Sony Computer Entertainment Inc. Memory protection system and method for computer architecture for broadband networks

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63165854A (en) * 1986-12-27 1988-07-09 Hamakawa Wataru Exposing device

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002077838A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Resource dedication system and method for a computer architecture for broadband networks
WO2002077845A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
WO2002077848A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
WO2002077846A1 (en) * 2001-03-22 2002-10-03 Sony Computer Entertainment Inc. System and method for data synchronization for a computer architecture for broadband networks
US6809734B2 (en) 2001-03-22 2004-10-26 Sony Computer Entertainment Inc. Resource dedication system and method for a computer architecture for broadband networks
US6826662B2 (en) 2001-03-22 2004-11-30 Sony Computer Entertainment Inc. System and method for data synchronization for a computer architecture for broadband networks
US7720982B2 (en) 2001-03-22 2010-05-18 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
US7457939B2 (en) 2001-03-22 2008-11-25 Sony Computer Entertainment Inc. Processing system with dedicated local memories and busy identification
US7093104B2 (en) 2001-03-22 2006-08-15 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
US7139882B2 (en) 2001-03-22 2006-11-21 Sony Computer Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
US7231500B2 (en) 2001-03-22 2007-06-12 Sony Computer Entertainment Inc. External data interface in a computer architecture for broadband networks
US7233998B2 (en) 2001-03-22 2007-06-19 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
KR100847982B1 (en) * 2001-03-22 2008-07-22 가부시키가이샤 소니 컴퓨터 엔터테인먼트 Resource dedication system and method for a computer architecture for broadband networks
US7461207B2 (en) 2002-05-06 2008-12-02 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
US7024519B2 (en) 2002-05-06 2006-04-04 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
US7870340B2 (en) 2002-05-06 2011-01-11 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
JP2006107514A (en) * 2004-10-05 2006-04-20 Sony Computer Entertainment Inc System and device which have interface device which can perform data communication with external device

Also Published As

Publication number Publication date Type
JPS6124738B2 (en) 1986-06-12 grant

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