JPS6124738B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inter-processing device data transfer method for transferring data between a plurality of processing devices via other processing devices.

A conventional data transfer method between processing devices is performed using a configuration as shown in FIG. That is, a first processing device 1 having a central processing device 4 and a storage device 6, a second processing device 2 having a central processing device 5 and a storage device 7, and these processing devices 1.
and 2, a third processing device 3 and a plurality of peripheral control devices 8 to N are used. Note that the first processing device 1
There is no direct connection between the processing device 2 and the second processing device 2.

Now, when an external storage device (not shown) is shared between the first processing device 1 and the second processing device 2, the usage status of the external storage device of each device is shared between both devices 1 and 2. will need to be replaced.

If this exchange is to be performed asynchronously, it is necessary to make effective use of the third processing device 3.

The operation of the conventional data transfer method using this third processing device 3 will be described below.

First, from the first processing device 1 to the second processing device 2
When attempting to transfer data to the third processing device 3, the first processing device 1 sends data transfer instruction information to the third processing device 3, and the third processing device 3 given this instruction information transfers data to the second processing device 3. Information notifying data transfer is sent to the processing device 2, and the second processing device given this notification information uses software to process whether or not it can receive the data, and the third processing device 3 The information instructing the processing device 2 to transfer the data is sent.

Details of this method are described in Japanese Patent Publication No. 49-35570. This method has the disadvantage that the entire data transfer time becomes long because software processing of the processing device 1 or 2 is always involved every time data is transferred.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for transferring data between processing devices that reduces the transfer time between the two devices that are attempting to transfer data.

The method of the present invention provides a data transfer method between processing devices in which data is transferred between a first processing device and a second processing device via a third processing device, and the method includes the step of transferring data to the third processing device. storage means for storing data, and when a write command instructing data transfer is given from the second processing device after a read command is given from the first processing device, the data is transferred from the second processing device. After the stored data is stored in the storage means, a read command from the first processing device is executed, and after a write operation is performed based on a write command given from the first processing device, the data is stored in the storage means. 2
When a read command is given from the processing device, the read operation is executed in response to the supply, and when a command other than the combined commands is given, the operation is performed based on that command. It is characterized by

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

The method of the present invention is characterized by the configuration of the third processing device 3 interposed between both devices 1 and 2.

This third processing device 3 includes a transfer circuit 10 that shares data transfer from the second processing device 2 to the first processing device 1, and a transfer circuit 10 that transfers data from the first processing device 1 to the second processing device in the opposite direction. Transfer circuit 11 that shares data transfer for 2 and both devices 1 and 2
The commands given from the two transfer circuits 10 and 11
It is composed of a command distribution circuit 12 that distributes the commands to the following.

The transfer circuit 10 and the transfer circuit 11 have the same logical circuit configuration except for the data transfer direction. Therefore, the command distribution circuit 12 and transfer circuit 11 will be explained below. The command distribution circuit 12 is the first
It is connected to a data transfer path that transfers data from the second processing device 1 and a data transfer path that transfers data from the second processing device 2, and after receiving commands from both data transfer paths and decoding them. , are supplied to transfer circuits 10 and 11. The transfer circuit 11 is
2 registers 114 and 115, 3 gates 112, 113 and 116, 4 flip-flops 1110, 1111, 1112 and 1
113, 4 AND elements 1114, 1115,
1116 and 1117, two decoders 117
and 118, two timer circuits 1118 and 1120, a buffer 111 for temporarily storing transfer data, a circuit 119 for controlling writing to and reading from the buffer 111, and a first processing unit for notifying the completion of a certain operation. 1 and a circuit 1119 that reports to the second processing device 2.

If the command sent from the command distribution circuit 12 is a write command, it is stored in the write command register 114 through the gate 112, and if it is a read command, it is stored in the read command register 115 through the gate 113.

When a command is stored in the write command register 114, the flip-flop 1111 is set to indicate acceptance of a write command via line R2, and when a command is stored in the read command register 115, line R3 is set.
A flip-flop 1112 is set up to accept and display a read command. The commands stored in these command registers 114 and 115 are decoded by decoders 117 and 118, respectively, and provided to control circuit 119. Based on the result of decoding the command given to the control circuit 119, a write operation or a read operation to the buffer 111 is performed. When this operation is completed, wire the signal indicating the end.
BW to flip-flop 1110 to indicate the end of a write operation, or line BR to flip-flop 1113 to indicate the end of a read operation to respective flip-flops 1110 and 1.
Set 113.

Among these flip-flops, if the flip-flop 1110 that indicates the completion of the write operation is set and the flip-flop 1113 that indicates the completion of the read operation is not yet set, the first timer circuit 1118 is activated when a predetermined time has elapsed since the setting. A signal indicating that from the line TO
Send to 1. In addition, the flip-flop 111
0 does not indicate the completion of the write operation, that is, when the signal is output to the line F10 and the flip-flop 1112 indicates the reception status of the read command, the second timer circuit 1120 is set and a predetermined time elapses. Line the signal to display the progress after
Send to TO2. These lines TO1 and TO2
The signal is applied to the completion report transfer circuit 1119 via the transfer circuit 1119, and the transfer circuit 1119 sends the completion report signal to the first processing device 1 or the second processing device 2.

After sending this completion report signal, the transfer circuit 111
A reset signal is sent from 9 to bring each circuit in the transfer circuit 11 into an initial state.

Next, the operation will be explained in further detail.

1 First, the operation when a write command is given after a read command will be described.

1 In the initial state, gates 112 and 113 are open, gate 116 is closed, and each flip-flop 1110, 11
11, 1112 and 1113, timer circuits 1118 and 1120 are in a reset state. From the first processing device 1 to the command distribution circuit 1
The read command is stored and decoded in 2. The decoded command is passed through the gate 113 and stored in the read command register 115 as a read command.
One pulse is then generated on line R3. Read command acceptance display flip-flop 1112
is set, the output F31 becomes "1" and the gate 113 is closed. AND circuit 1117
Since the write operation is not performed while the read command is being accepted, the output becomes “1” and the timer circuit 112
0 is set.

2 Below, the operation is divided into two depending on whether a write command is given within a certain period of time.

When a write command is not given, the timer circuit 1120 outputs a signal indicating this to the line TO2 after a predetermined time elapses, and the completion report transfer circuit 1119, which has been given this signal, returns each circuit in the transfer circuit 11 to the initial state. After setting, the first processing device 1 and the second processing device 2 are notified that a predetermined time has elapsed with a read command. After this, the supply of read commands is stopped.

When a write command is given, the command is stored in the write command register 114 from the command distribution circuit 12 via the gate 112, decoded by the decoder 117, and a write operation to the buffer 111 is started. At the same time, one signal is sent to line R2. This signal sets the flip-flop 1111 which is accepting a write command, and the gate 112 is closed. When the write operation to buffer 111 is completed, a signal is sent from control circuit 119 to line BW. This signal causes the flip-flop 1110 to complete writing.
is set, and the line F11 becomes "1". When the write operation is completed and there is no read operation, the timer circuit 1118 is set and the operation starts.

At this time, if the write operation is completed and a read command is being accepted, the gate 116 is opened.
The read command held in the read command register 115 until the write operation is completed is decoded by the decoder 118 via the gate 116, and the read operation from the buffer 111 is started. When this read operation is completed, a signal of 1 is sent from the control circuit 119 to the line BR.
The read end flip-flop 1113 is set and the output F41 becomes "1". When the write operation is completed, the output F11 of the flip-flop is "1" and the output F11 is "1".
Since 41 is “1”, AND gate 11
15 becomes "1". As a result, each circuit in the transfer circuit 11 is set to an initial state from the completion report transfer circuit 1119, and a normal completion report signal is sent to the first processing device 1 and the second processing device 2.

2 Next, the operation when a read command is given after a write command will be described.

1 The initial state is the same as 1 above. First, a write command from the first processing circuit 1 is stored in the command distribution circuit 12 and decoded.

A write command is stored from this command distribution circuit 12 into a write command register 114 via a gate 112. Along with this storage, a signal is supplied to the line R2, and the result decoded by the decoder 117 is given to the control circuit 119 to start the write operation. The write command receiving flip-flop 1111 is set by the signal applied to the line R2, and the gate 112 is closed. Upon completion of the write operation, control circuit 1
A signal is sent from line BW from 19 to set write end flip-flop 1110 and output to line F.
11 becomes 1 and the read end flip-flop 1113 is in the reset state, so the timer circuit 1118 starts operating.

2 There are two types depending on whether the read command is given within a certain period of time.

1 When a read command is not given When a signal indicating the passage of time is generated in the timer circuit 1118, it is given to the completion report transfer circuit 1119 via the line TO1, and after setting each circuit in the transfer circuit 11 to the initial state, the write It reports to the first processing device 1 and the second processing device 2 that the time has elapsed due to the command.
The write command is then aborted.

2. When a read command is given A read command is stored in the read command register 115 from the command distribution circuit 12 via the gate 113. A signal is generated on the line R3, the read command flip-flop 1112 is set, and the output F31 becomes "1". Along with this, the write end flip-flop 1110
is set to "1", the gate 116 is opened via the AND gate 1116, the stored read command is decoded by the decoder 118, and the control circuit 119 starts the read operation. After the read operation is completed, the operation is similar to the operation in item 1 above.

From the above points, by equipping the third processing device 3 with the circuit shown in FIG. 2, if a write command is given when a read command is given to the third processing device 3 in advance, the read command will be issued immediately after the write operation. execution begins. Further, if a read command is given to the third processing device 3 when a write command has been given in advance, the contents already stored in the buffer 111 can be immediately read out.

As explained above, in the present invention, by giving a read command to the third processing device in advance, as soon as the data transfer process of the write command is completed, the read command is immediately given without the intervention of software processing on the receiving side. Can perform data transfer processing,
This has the effect of reducing data transfer time between processing devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG.
The figure is a diagram showing a transfer circuit within the third processing device in FIG. 1. 1 and 2, 1... first processing device, 2... second processing device, 3... third processing device, 4, 5... central processing unit, 6, 7... Storage device, 8 to N... Peripheral control device, 111... Buffer, 112, 113, 116... Gate, 1
14...Write command register, 115...Read command register, 117, 118...Decoder, 1
19...Control circuit, 1110-1113...Flip-flop, 114-117...AND element,
1119... Completion report transfer circuit, 1118, 11
20...Timer circuit.

Claims (1)

[Scope of Claims] 1. A data transfer method between processing devices in which data is transferred between a first processing device and a second processing device via a third processing device having data storage means, comprising: When a write command instructing data transfer is given from the second processing device after a read command is given from the first processing device, the data transferred from the second processing device is stored in the storage means. a first process in which the third processing device executes a read command from the first processing device; and a first process in which the third processing device executes a write operation based on a write command given from the first processing device; 2
and a second process in which the third processing device executes the read operation when a read command is given from the third processing device.