JPS589274A - Write data buffer control device - Google Patents

Abstract

PURPOSE:To improve the capacity of a write data buffer control device by providing a cancel control circuit and making time relation between write request and write data free for write request from an executable unit to a memory. CONSTITUTION:When a cancel permit signal 33 from an access control section is ''1'', a cancel control circuit 14 resets the data significance display bit of a read pointer register 13 and a write pointer register 12 to an initial state. When the cancel permit signal 33 is ''0'', the circuit makes a cancel waiting FF60 ''1'' and waits until the permit signal 33 becomes ''1''. Logical sum of a write cancel start signal 35 and a cancel waiting signal 36 is taken in a gate 61, and a cancel designation signal 34 is sent to a memory access control section. By this way, time relation between request and write data for write request from an executable unit to a memory can be made free, and thus capacity of the write data buffer control device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a write data batzer□ control device.
□ In general, when the second execution block including the first arithmetic control circuit and the preemption control circuit performs a write operation to memory, a write request code, '*i address J write data, etc. It is necessary to make a write request to the access enumerator.

At the end of this memorization process, the logical address is converted into an execution address and the write data is written into the memory corresponding to the obtained real address. Here, in a device having a bar 77 memory, the write data is also written to the bar memory.

These write operations are rounded and pipelined to speed up the operation.
It is processed.

The conventional write data parser 721 control device has the necessity to flow write requests, write addresses, and write data simultaneously or one after another while maintaining a fixed time relationship. must be sent to the memory access unit at the same time or in a fixed relationship with the write request and write address.

On the other hand, in the execution unit, there are cases where the write data is determined before the write address, and conversely, where the write address is determined first, but in both cases, the write data is determined before the write address. The drawback was that it was necessary to make sure that there were no exceptions that would be prohibited, so it had to be decided later.

For example, when a write address is determined, if it is possible to advance the conversion from a logical address to a real address in the memory access unit by issuing a request to the memory access unit, the performance will improve. The improvement was remarkable, but the effect like that of Hi was not as expected.

An object of the present invention is to eliminate the time relationship between write requests from execution units and write data, and to prevent write requests from being issued until the write data is prepared. It is an object of the present invention to provide a write data buffer control device which avoids performance deterioration due to not being able to send write data until a write address is determined.

A write data buffer control device of the present invention includes a write data buffer that parses write data to a memory;
In response to a storage request from an execution unit to the write data buffer, if there is no space in the write data buffer, it is rejected; if there is space, a storage location is determined, and the write data is stored at the determined storage location. At the same time, the write data buffer control circuit makes the data in the ζO storage location valid, and the write data buffer control circuit makes the data in the ζO storage location valid, and in response to the start of writing to the memory, the write data buffer control circuit makes the data in the ζO storage position valid. ) It is determined whether the storage location of γ is in a valid state or not, and if it is valid, writing to the memory is started, and then the valid state is canceled. , and a Jansell control circuit for suppressing the start of writing.

6. The write data puffer control device of the present invention responds to the memory access cancellation signal from the execution unit by the cancel control circuit, determines the valid state of the data and the state of start of writing to the memory, and processes the data. The configuration is such that at least one of the valid state and the write request to the memory can be canceled.

That is, the write data buffer control device of the present invention sets the write f-fi buffer in the memory access unit, and stores the data in response to the storage request from the execution unit to the data buffer if there is space in the buffer. Determine the location and sequentially store the write data; simultaneously set the data for the area to a valid state 2; and convert the logical address to a real address in the MII in the memory access unit in response to a memory access request initiated by the execution unit with the address. Complete If the access request is to write to memory, retrieve the data sequentially from the write data buffer.If the data is valid at this time, start writing to memory and wait for completion of sending to memory. resets the valid state of the data, but if the data is not valid, it suppresses activation to the memory until it becomes valid, and the memory access unit receives at least one of the write request and the write data. The execution unit is configured to have a function of rejecting the write data and write request in response to a write cancel signal generated when the execution unit detects an exception in the write operation.

Next, what about the embodiments of the present invention? ) l/m will be explained in detail with reference to WJWl.

FIG. 1 is a system configuration diagram including a write data buffer control device of the present invention, where 1 is an execution unit, 2 is a memory access unit, and 3 is a memory. Contains equipment.

No.'Nl! J represents an embodiment of the present invention! In the evening view, there are nine write data bars of the present invention provided in the memory access unit 2! FIG. 2 is a schematic diagram showing an outline of a firmware control device.

Execution unit 1 sends the write data to the memory access control unit)
2, the write data 22 is supplied and the strobe signal 21 is set to 11@ to activate the write data buffer control circuit IO.

If the J write data buffer 7711 is not full, the write data buffer control circuit 10 sends an acceptance notification signal 29 (IK) to notify that the write data 22 has been accepted. At the same time, the address 31 stored in the write pointer register 12) write data buffer 1.
The write data 22 is written in the word position 1, the write data valid display period of the blank word is set to @l'', and the write pointer register 12 is passed.

On the other hand, another control unit (not shown in the figure) of the memory access control unit 2 processes the memory access request received at any timing from the execution unit 1 and obtains the real address for the logical address. Writing or reading is determined at the time, and the state of the write instruction signal 28 is determined. The instruction signal 28 is the result of the logical product negation of whether all of the data valid display bits 40 are @0'' at the gate 43.
), if the write data valid indication bit of the word indicated by the read pointer register 13 is 10, it becomes @1''.

FIG. 3 shows the write data path control circuit 1 shown in FIG.
0 is a circuit diagram showing details of an example of the write data pub file 1.
The case where the number of words in 1 is 4 will be shown.

Data valid display beep) 4G is write data badafa! It has l bit ψ for each word of 1, valid at '1', @0
° indicates invalid.

When the strobe signal 2 from the execution unit 1 becomes valid, the gate 42 opens when the data valid display pins 40 are not all @1'', that is, when the write data buffer 11 is not full. When the output of the decoder 41 is valid by the address 31, the data valid indicator bit 40 of the word indicated by the write pointer register 12 is set to "L". This shows the valid state of the write data 22 corresponding to the write request.This write data buffer 11 is controlled to be read in the order in which it was written, so if the instruction signal 2B is valid, the address 25 is It is guaranteed that the read data position data valid display bit 40 shown by is at least valid.

If the instruction signal 22 sent to the memory access control section is valid, O writing to the memory 3 is started, and upon completion, the instruction signal 27 is made valid. As a result, the output of the decoder 440 becomes valid, and the data valid display pin 4G of the word indicated by the read pointer register 13 is reset. Additionally, the read pointer register 134 is read.

FIG. 4 is a circuit diagram showing details of an example of the cancel control circuit 14 shown in FIG. 2 @Execution unit! During the writing process, Jansel is activated by the write cancel activation signal 35.

In the cancel control circuit 14, if the cancel permission signal 33 from the memory access control section is @11''Im, the data valid display bit v) of the read pointer register 13 and the write pointer register 12 is set to the initial state by the Jansel signal 32. Reset.

When the cancel permission signal 33 is @0 @, the cancellation wait flip ψ 70 drop program is set to 0t"l@, and waits until the cancel permission signal 33 becomes 11". Further, the write cancel activation signal 35 is logically summed with the cancel wait signal 36 at a gate 61, and a cancel instruction signal 34 is sent to the memory access control section.

The cancel permission signal 33 from the memory access control unit is activated when the memory access controller 2 completes the conversion from a logical address to a real address and starts writing to the memory 3 with the write data 22 also in a valid state. 3 is in use, so activation may have to wait temporarily, but only in this case is it invalid.) Otherwise, it is controlled so that it is always valid.

By adding a cancel control circuit, the write data bar t77 control device of the present invention can freely set the time relationship between the write request and the write data in response to the O write request from the execution unit to the memory. This has the effect of improving the weight performance.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram including a write data pad 977 control device of the present invention, and FIG. ! A block diagram showing an embodiment, FIG. 3 is a circuit diagram showing details of an example of the write data bar 977 control circuit shown in FIG. 2, and FIG. 4 shows details of an example of the middle Jansel control circuit shown in FIG. 2. It is a circuit diagram. 1...Any execution, 2...Memory access, 3...Memory, 4...
-Write data buffer control device %IO...Write data buffer control circuit, 11...Write data par J7a, 12. ...Write pointer register! 3... Read pointer register, 14...
...In the middle, #control circuit, 40...Data valid display bit, 41...Decoder, 42...
...Gate%43...Gate, 4゛4...
... Decoder, 60 ... Cancellation wait 7 lip flop, 61 ... Gate, 21 ... Strobe signal, 22 ... Write data, 23 ... ...7) '1/J, 25...
...Address, 27...Instruction signal, 28...
...Instruction signal, 29...Reception notification signal, 3
1...address, 32...cancel signal, 3a...middle Jansel permission signal, 34...
...Cancel instruction signal, 35...Yansel activation signal during writing, 36...Cancellation wait signal.

Claims (1)

[Claims] (1) A write data buffer for buffering write data to the memory, and storage from the execution end to the write data path 97a, g! In response to the request, the write data bar γ is rejected as there is no space, and if there is space, a storage position is determined, and the write data is stored in the determined storage position, and the data at this storage position is valid. In response to the start of writing to the supplementary memory, the control circuit determines whether the storage position of the write data buffer is in a valid state, and if it is valid, starts writing to the memory. The write data controller is characterized in that it includes a cancel control circuit for canceling the valid state and suppressing the start of the write operation until the valid state is reached. Fa control device. (2. The cancel control circuit described in claim (1) responds to the memory access dissipation signal from the execution unit and determines the valid state of the data and the state of writing to the memory. 'cancel' the valid state of
- A write data buffer control device. □.