JPS6239788B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control method in a channel device that can prevent command overruns.

FIG. 1 shows a recording format in a disk pack device, and FIG. 2 shows an example of exchange of interface signals between a channel and a disk pack device. In the case of a read, when the disk pack device has one byte of data ready, it puts the data on the bus-in line and turns on the service-in SVI. When the channel device receives the data, it goes out of service.
Turn on SVO. When the disk pack device turns on the service-out SVO, it drops the service-in SVI, and the channel device drops the service-in SVI.
When the in SVI drops, the service out SVO drops. When the next byte of data is ready, the disk pack device places the data on the bus in line and turns on the data in DTI. When the channel device receives data, it turns on the data out DTO. A disk pack device drops its data in DTI when its data out DTO is turned on, and a channel device drops its data out DTO when its data in DTI falls. When the next byte of data is ready, the disk pack puts the data on the bus in line and sends it to the service in SVI.
Turn on. When one block of data has been transferred and the head is passing through the gap between the data, the disk pack device places the status on the bus in line, turns on the status in STI, and When the channel device receives the status, it turns on Service Out SVO. Furthermore, upon receiving the status in, the channel device checks the status, and if the status indicates normal completion and the command chain flag is logic "1", it reads the next command from the main memory and executes the read command. The disk
send to the pack device. This command chaining must occur while the head is passing through the gap between data, but the disk drive must not receive new commands while the head is passing through the gap. First, if a new command is received after the head has reached the data recording area, a command overrun occurs and execution of the new command is waited until the disk rotates once. Generally, in disk pack devices,
A considerable amount of time is required between when the head enters the gap and when the status input is turned on. In conventional channel devices, if read data sent from the disk pack device remained in the channel at the time of receiving the status in, this remaining data was stored in the main memory. Since the next command is read from the main memory later, it has the disadvantage that command overruns are likely to occur.

The present invention eliminates the above-mentioned drawbacks by storing the read data remaining in the channel device in the main memory before a signal indicating that a command can be received from the input/output device is received. The purpose of this invention is to provide a data transfer control method in a channel device that can prevent command overruns. Therefore, the data transfer control method in the channel device of the present invention is
A channel device that controls data transfer between an input/output device and a main memory device has a time monitoring enable flag in a subchannel memory that has a one-to-one correspondence with the input/output device, and the time monitoring flag is enabled. In addition, when data is being transferred from the input/output device to the main storage device, if there is no data transfer request from the input/output device for a certain period of time,
It is characterized by storing the data previously received from the input/output device into the main memory. Hereinafter, the present invention will be explained with reference to the drawings.

FIGS. 3A and 3B are block diagrams showing one embodiment of the present invention. FIG. 3A mainly shows the part that handles data, and FIG. 3B mainly shows the control part. In Figure 3 A and B, 1-0 is the bus-in 0 register, 1-1 is the bus-in 1 register,
2 is a data buffer storage, 3 is a data buffer register, 4 is a data address counter, 5 is a decoder, 6 is a command register, 7 is also a decoder, 8 is a time monitoring timer, 9
is a decoder, 10 is a flip-flop, 11 is a subchannel memory, 12 to 14 are AND
The circuits 15 and 16 are OR circuits, RD is a read command, and RB is a read backward command.

Next, the operation of the embodiment shown in FIG. 3 will be explained. In Fig. 3A, data sent from an input/output device, such as a disk pack device, is sent to data buffer storage 2 via bus in 0 register 1-0 and bus in 1 register 1-1. Stored. Data buffer storage 2
The data is read out one byte at a time, and the data
It is set at the byte position of data buffer register 3 indicated by address counter 4.
The value of data address counter 4 is incremented by 1 every time data is written to data buffer register 3. When data is stored in all of the 0-byte to 3-byte positions of data buffer register 3, this 4-byte data is sent to the main memory, and then the data read from data buffer storage 2 is stored. is a data buffer.
Stored in 4-byte position of register. data·
When data is stored in all 4 to 7 byte positions of buffer register 3, these 4
The byte of data is sent to main memory and the data read from data buffer storage 2 is then written to the 0 byte location of data buffer register 3.

Next, the operation of the apparatus shown in FIG. 3B will be explained.
Commands retrieved from main storage are
It is set in register 6 and analyzed by decoder 7. When the command is a read command or read backward command, AND
A logic "1" is input to the upper input of the circuit 12. Subchannel memory 11 has input/output devices and 1
It is provided in a one-to-one correspondence,
Various control information regarding the corresponding input/output device is stored in this. Subchannel memory 11
A timer valid flag is also written to the input/output device, and if the input/output device is of a certain type, such as a disk drive, the timer valid flag is set to a logic "1". This timer
A valid flag is set in flip-flop 10. Therefore, when the command being executed is a read command or a read backward command and the timer valid flag is logic "1", the AND circuit 12 is logic "1".
Output. When the AND circuit 12 is at logic “1” and data is being transferred, the AND circuit 14
opens. Note that data is being transferred when the status input STI is sent after the channel and input/output device are connected.
This means the period until it turns on. AND
When the circuit 14 is on, the value of the time monitoring timer 8 is incremented by 1 every time a unit of time elapses. If data is being transferred when an I/0 data transfer request (service in or data in) is sent,
The AND circuit 14 opens and all "0"s are set in the time monitoring timer 8. The timer value of the time monitoring timer 8 is analyzed by the decoder 9, and if the value is a predetermined value, a store request is sent to the main storage device via the OR circuit 15. When this request is accepted, data buffer register 3
4 stored in the 0 byte position to 3 byte position or the 4 byte position to 7 byte position of
Data smaller than a byte is stored in main memory.

As is clear from the above explanation, according to the data transfer control method of the channel device of the present invention, each time there is a data transfer request during data transfer, the time monitoring timer is cleared and time monitoring is restarted. When the timer value reaches a predetermined value, the data in the channel device is forcibly stored in the main memory, so the data in the channel device is forcibly stored in the main memory. read data can be stored in the main memory, and as a result, the occurrence of command overruns can be significantly reduced compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a recording format in a disk pack device, FIG. 2 is a diagram showing an example of the exchange of interface signals between a channel and a magnetic disk pack device, and FIG. FIG. 1 is a block diagram showing one embodiment. 1-0...Bus in 0 register, 1-1...
Bus in 1 register, 2...Data buffer storage, 3...Data buffer register, 4...Data address counter, 5...
...Decoder, 6...Command register, 7...
Decoder, 8...Time monitoring timer, 9...Decoder, 10...Flip-flop, 11...Subchannel memory, 12 to 14...AND circuit, 15 and 16...OR circuit, RD...Read command , RB...Read backward command.

Claims (1)

[Claims] 1 A channel device that controls data transfer between an input/output device and a main storage device has a time monitoring enable flag in a subchannel memory that has a one-to-one correspondence with the input/output device, and the time monitoring flag is enabled. and when data is being transferred from the input/output device to the main storage, if there is no data transfer request from the input/output device for a certain period of time, the data received from the input/output device until then is transferred to the main memory. A data transfer control method in a channel device characterized by storing data in a storage device.