JPH064489A - Communication system among plural cpu - Google Patents

Abstract

PURPOSE:To shorten communication waiting time among plural CPUs. CONSTITUTION:The CPU 20 for address management manages the addresses of an A/D converter 12, a D/A converter 16 and a picture memory 14. A recording/reproducing control circuit 24 controls a rotating drum and a tape traveling system and the CPU 20 for communication mediates the communication between the recording/reproducing control circuit 24 and the CPU 20 for management. The I/O part of the CPU 26 is connected through a control line 30 to the IRQ port of the CPU 20 and the I/O port of the CPU 20 is connected through the control line 32 to the IRQ port of the CPU 26. The CPU 20 and 26 interrupt the other CPU 26 or 20 on the reception side when the communication is required. Information to be communicated is transferred through an instruction memory 20 which is a dual port memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system for communicating between a plurality of CPUs.

[0002]

2. Description of the Related Art In recent years, microcomputers have come to be used in various electric and electronic devices because they can easily realize complicated functions or controls by their operation programs, and further, individual circuit modules have individual microcomputers. A circuit configuration has been used, which is controlled by a computer (or CPU), and the CPUs are connected by a common data / address bus or a dedicated communication line. When communication is discontinuous or non-steady, normally, necessary information is communicated between CPUs by interrupt processing.

[0003]

However, for example, when the transmitting side CPU or the receiving side CPU is executing complicated processing and the control information or the like cannot be immediately communicated from the transmitting side CPU to the receiving side CPU due to an interrupt, the transmitting side CPU Both the receiving CPU and the receiving CPU must wait until communication becomes possible. This results in wasted waiting time and a substantial reduction in execution speed.

It is an object of the present invention to provide a communication system between a plurality of CPUs which solves such inconvenience.

[0005]

Multiple CPUs according to the present invention
In the communication system between the CPUs, the input / output ports and the interrupt request input ports are connected to a plurality of CPUs, and a memory means for temporarily storing communication information is arranged between the CPUs so that the CPUs on the transmitting side and the receiving side The CPU is interrupted, and the communication information is transferred from the transmitting side CPU to the receiving side CPU via the memory means.

[0006]

By the above means, the transmitting side directly interrupts the receiving side, so that the communication can be started immediately when necessary.
Further, since the information to be communicated is transferred through the dedicated memory means, the information can be delivered and received quickly. As a result, the waiting time for communication can be shortened and the utilization efficiency of each CPU can be improved.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of the present invention applied to a moving picture recording / reproducing apparatus, a so-called video tape recorder.

In FIG. 1, 10 is an input terminal for a video signal to be recorded, 12 is an A / D converter for digitizing an analog video signal from the input terminal 10, and 14 is an image to be recorded or reproduced. An image memory for temporarily storing a signal, 16 a D / A converter for converting a reproduced digital video signal into an analog signal, and 18 a D / A converter 1
6 is an output terminal for outputting the output (reproduced video signal) of 6 to the outside. An address management CPU 20 manages the addresses of the image memory 14 and controls the A / D converter 12 and the D / A converter 16. A / D converter 12, D /
A converter 16, image memory 14, and CP for address management
U20s are interconnected via a data / address bus 22.

Reference numeral 24 is a recording / reproducing control circuit for controlling the rotating drum, tape running system and the like, and 26 is a recording / reproducing control circuit 2.
4 is a communication CPU that mediates communication between the address management CPU 4 and the address management CPU 20. 28 is an address management CPU 20
Is a command memory that stores control information (commands and frame numbers) for communication between the communication CPU 26 and the communication CPU 26, and includes a dual port memory that can be read and written by both the address management CPU 20 and the communication CPU 26.

Input / output (I / I) of the communication CPU 26
O) Port is a CP for address management via the control line 30.
It is connected to the interrupt request (IRQ) port of U20, and the I / O port of the address management CPU 20 is connected to the IRQ port of the communication CPU 26 via the control line 32.

The operation of this embodiment will be described. The recording / reproducing control circuit 24 controls the rotating drum and the tape running system in accordance with the recording / reproducing of the moving image and the special reproduction such as the slow reproduction and the still image reproduction.
Output to PU26. The communication CPU 26 transmits an ACK signal and a tally signal to the recording / reproducing circuit 24.

The address management CPU 20 is an image memory 1
No. 4 address is controlled and the A / D converter 12 and the D / A converter 16 are controlled so that the video signal input from the input terminal 10 is stored in the image memory 14 and reproduced from a recording medium (not shown). The operation of reading the video signal stored in the image memory 14 and externally outputting it from the output terminal 18 is controlled and controlled.

Communication CPU 26 and address management CPU
The 20s operate independently of each other and do not interfere at all in the normal running state except when communicating with each other. Figure 2
Shows an operation flowchart of the communication CPU 26 and the address management CPU 20. The communication management CPU 26 is exclusively in communication with the recording / reproduction control circuit 24 (S1), and the address management CPU 20 is in address management of the image memory 14 (S11). The communication CPU 26 and the address management CPU 20 communicate with each other by the communication CPU.
26 is when a command relating to recording / reproduction is input from the recording / reproduction control circuit 24 (S2), while for the address management CPU 20, a tally signal or an abnormal signal from the image memory 14 or a peripheral device is input. (S12).

For example, when a recording / playback command is transferred from the recording / playback control circuit 24 to the communication CPU 26, the communication CPU 26 writes the frame number of the moving image and the command content in the command memory 28 (S3), and the control line. An interrupt command is transmitted to the address management CPU 20 via 30 (S4). In response to this, the address management CPU 20
The operation currently being executed is forcibly interrupted, and the interrupt routine is started (S15).

In the interrupt routine of the address management CPU 20, the frame number and the instruction content are read from the instruction memory 28 (S16), the address of the image memory 14 is calculated from the read frame number, and the image memory, A The / D converter 12 and the D / A converter 16 are operated (S17). When the process of the interrupt routine is completed, the process returns to the main routine (S18) and the operation before the interrupt is continued.

When the address management CPU 20 receives a tally signal or an abnormal signal from the image memory 14 and other peripheral devices (S12), the contents and frame number are written in the instruction memory 28 (S13), and the control line 32 is set. The CPU 26 for communication is instructed to make an interrupt (S14). In response to this, the communication CPU 26 interrupts the operation currently being executed and starts the interrupt routine (S5).

In the interrupt routine of the communication CPU 26, the frame number and communication information are read from the instruction memory 28 (S6), and the communication information is transferred to the recording / reproducing control circuit 24 (S7). After this, return to the main routine (S
8) Continue the operation before interruption.

In this way, by connecting the I / O ports and IRQ ports of the CPUs 20 and 26 to each other, it is possible to forcibly perform various operations when necessary by interrupts without interfering with the operations of the individual CPUs. it can. As a result, the main routine of each CPU 20, 26 can be simplified, and it is not necessary to confirm the mutual operation states at all times or when necessary, and the time lag of instruction execution can be shortened. As a result, the execution time can be significantly reduced.

[0020]

As can be easily understood from the above description, according to the present invention, the communication time between a plurality of CPUs can be shortened and each CPU can be operated efficiently.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is an operation flowchart of this embodiment.

[Explanation of symbols]

10: Input terminal 12: A / D converter 14: Image memory 16: D / A converter 18: Output terminal 20: Address management CPU 22:
Data / address bus 24: recording / reproduction control circuit 2
6: Communication CPU 28: Instruction memory 30, 32: Control line

Claims (1)

[Claims] 1. A plurality of CPUs are connected to each other's input / output ports and interrupt request input ports, and C
A memory means for temporarily storing communication information is arranged between PUs,
A communication system between a plurality of CPUs, characterized in that the transmitting CPU interrupts the receiving CPU to transfer communication information from the transmitting CPU to the receiving CPU via the memory means.