JPS6161432B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output channel device in a data processing device.

Conventionally, the data transfer system used in the input/output interface between the input/output channel device and the input/output control device is controlled by tag lines that ensure the integrity of the data on the data line. For example, in data transfer from an input/output control device to an input/output channel device, the input/output control device establishes data on the data line and transfers the tag line A to the input/output channel device.
Data is sent by setting the logic to "1".

When the tag line A becomes logic "1", the input/output channel device takes in the data on the data line and notifies the input/output control device through the tag line B that the data has been received. The input/output control device recognizes that the data on the data line has been received by the notification on the tag line B, and sends the next data to the input/output channel device in the same procedure as above.

During data transfer from an input/output channel device to an input/output control device, the input/output control device requests the input/output channel device to transfer data via tag line A, and the input/output channel device transfers data on the data line based on the request on tag line A. The tag line B is set to logic "1" by putting data on it. The input/output control device takes in the data on the data line with the logic "1" on the tag line B, and requests the transfer of the next data using the tag line A.

As described above, in this conventional transfer method, each device checks the response of tag line A or B and proceeds with the transfer sequence, so it is not possible to make the data transfer speed sufficiently high, and the cable length between the two devices is too long. There was a drawback that the longer the length, the lower the transfer speed.

On the other hand, as the recording density of input/output devices such as magnetic disk devices increases, the transfer speeds required for these devices tend to increase, and the transfer capability of the input/output interface needs to be improved. Therefore, as a means of achieving high transfer speed, a method has been used in which a transfer operation is performed without confirming the response of the tag line, as shown below.

In this conventional system, as shown in FIG. 1, the input/output control device continuously requests or transfers data via the tag line A without waiting for a response on the tag line B from the input/output channel device. 1st
The figure shows the case of input transfer from an input/output channel device to an input/output control device. When the input/output control device raises the signal on tag line A and requests data transfer from the input/output channel device, without waiting for a response from the input/output channel device using the signal on tag line B,
When a predetermined period of time t has elapsed,
As long as the next data can be accepted, data is requested one after another by the signal on the tag line A. The input/output channel device receives the signal on the tag line A, and when the data is ready, places the transfer data on the data line and sends the signal to the tag line B. The input/output control device confirms the response to the previous request using the signal on the tag line B, and also takes in the data on the data line.

According to this conventional method, data can be transferred in t cycles without waiting for a response from the other device, so it has the advantage of being able to perform high-speed transfer processing, but on the other hand, the control mechanism for controlling this interface is complicated. There is a drawback.

The purpose of this invention is to increase the number of accepted signals of tag line A,
We have developed an input/output channel device that solves the above drawback by managing the difference between the number of signals sent from tag line B and allows easy control of the input/output interface that performs high-speed transfer without requiring response confirmation. It is about providing.

According to this invention, the number of receptions of the tag line A signal sent from the input/output control device, and the tag line B sent to the input/output control device in response to the tag line A signal.
and a means for counting the difference between the number of transmitted signals and means for transmitting the signal of the tag line B when the difference is not zero.

Next, embodiments of the invention will be described with reference to the drawings.

FIG. 2 is a system configuration diagram showing an embodiment of the present invention. In FIG. 2, a central processing unit (hereinafter referred to as CPU) 30 is connected to a main memory unit (MMU) 10 via a main memory control unit (MCU) 20.
A channel program is stored therein, and the input/output channel control device (IOCHC) 40 is instructed to start input/output operations. Input/output channel control device 40
consists of a channel control unit (CHC) 41 and a plurality of input/output channel devices (CH) 50 to 57, and each input/output channel device is connected to an input/output control device (CHC) by an input/output interface path 110 to 117. IOC) 60 to 67 are connected. Further, input/output units (IOU) 70 - 77 are connected to each input/output control device 60 - 67 .

The channel control unit 41 reads the channel program on the main storage device 10 according to an input/output operation instruction from the CPU 30, and starts the input/output channel device specified by the program. Now, to explain the case where the input/output channel device 50 is specified by a program, the input/output channel device 50 transmits the input/output command specified by the program to the input/output control device 6.
0 to instruct the input/output device 70 to start up. When the input/output control device 60 and the input/output device 70 are activated, the input/output channel device 50 starts the transfer operation specified by the input/output command. That is, in the case of an input type command, data sent from the input/output control device 60 is stored in the address of the main storage device 10 specified by the channel program, and in the case of an output type command, the data is read from the main storage device 10 and sent to the input/output control device. Transfer to 60. Input/output channel device 5
The transfer operation at the interface 110 between the input/output controller 60 and the input/output controller 60 is performed according to the sequence shown in FIG.

The configuration of the input/output channel device 50 is shown in FIG. The input/output channel device 50 is a channel control section 8
0, input/output interface control unit 82, data buffer 81, and input/output interface register 8
4 and 85, and input/output operation instructions from the channel control section 41 are notified to the channel control section 80 through a path 1031. The channel control section 80 terminates the instruction command and instructs the input/output interface control section 82 to control the I/O interface for activating the input/output control device 60 via the path 201.

The I/O interface path 110 includes a control signal line group 1101, an output data line 1102 from the input/output channel device 50 to the input/output control device 60, and an input data line 1103 from the input/output control device 60 to the input/output channel device 50. It consists of I/
The O interface control unit 82 performs startup sequence control of input/output operations using the path 110, but the details of this operation are not directly related to this invention and will therefore be omitted.

Following the startup sequence, an input/output data transfer operation begins, and when input is transferred from the input/output control device 60 to the input/output channel device 50, the input/output control device 6
0 puts data on path 1103, and puts data on path 1101
The input/output interface control unit 82 sets the strobe signal 204 of the register 85 to logic “1” and transfers the data on the path 1103 to the register 85 according to the instruction of the tag line A. Incorporate into. The data taken into the register 85 is stored in the data buffer 81 and sent to the channel control unit 41 via a path 1032 to request storage in the main storage device 10. In addition, the input/output interface control unit 82 sets the tag line B on the path 1101 to logic "1" to notify the tag line A that data has been received.

From the input/output channel device 50 to the input/output control device 6
0, the input/output channel device 50 reads the output data from the main storage device 10 under the control of the channel control section 41 prior to the transfer operation.
It is stored in the data buffer 81. In the case of output transfer, when the input/output control device 60 becomes ready to receive data, it requests the data via the tag line A on the path 1101 and transfers the data to the input/output interface control section 82.
transfers data from data buffer 81 to register 8
4 and place it on the path 1102, and set the tag line B to logic "1" to transfer the data to the input/output control device 60.

During the above input and output transfer, the input/output control device 60
transfers or requests data one after another via the tag line A without waiting for a response from the input/output channel device 50 via the tag line B. The input/output channel device 50 has a register 83 with a counting function in the input/output interface control section 82.

The operation of this counter will be explained with reference to FIG. FIG. 4 is a time chart showing the opening relationship between the tag line and the counter. When a signal is received on the tag line A, the input/output interface control unit 82 increments the contents of the register with counting function 83 by 1, and the signal is applied to the tag line B. When the signal is sent, the register 83 is decremented by -1. Also
The BUF-RDY signal is a signal indicating whether data can be stored in the data buffer (during input transfer) or data is ready (during output transfer).

Now, regarding the case of output transfer, the register 83 is incremented by 1 every time the tag line A is accepted, but when the BUF-RDY signal becomes logic "1" and it is detected that the data to be transferred is prepared, The input/output interface control section 82 checks the state of the register 83 at that time, and if the value is positive, sends the data to the input/output control device 60 by the signal on the tag line B, and at the same time increments the contents of the register 83 by 1. below
As long as BUF-RDY=1 and the contents of the register 83 are positive, a signal on the tag line B is sent out at a predetermined constant cycle, and data is transferred to the input/output control device 60.

As described above, the input/output interface control unit 82 responds to data transfer requests from the input/output control device.
The response can be controlled via the register 83, and the condition for transmitting the signal on the tag line B can be determined based on the state of the register 83 without looking at the signal on the tag line A. Therefore, the control logic of the input/output interface can be created very easily, and the input/output control can be performed even if the data to be transferred to the input/output control device 60 is not ready in the data buffer 81 by waiting for access to the main storage device 10. Continuous data requests from device 60 can be handled.

As explained above, the present invention is applicable to a high-speed transfer method in which a sequence is advanced without confirming the tag line response during transfer between an input/output channel device and an input/output control device. By having a counter for managing the difference between the tag line A and the tag line B of its response, there is an effect that high-speed input/output transfer operations can be controlled very easily.

[Brief explanation of the drawing]

FIG. 1 is a time chart showing the transfer sequence of the input/output interface used in this invention.
FIG. 2 is a system configuration diagram showing an embodiment of the present invention, FIG. 3 is a block diagram showing details of the input/output channel device 50 shown in FIG. 2, and FIG. 4 is a time diagram showing the counter operation of the present invention. It is a chart diagram. 10: Main memory device, 20: Main memory control device, 3
0: central processing unit, 40: input/output channel control device, 41: channel control unit, 50, 57: input/output channel device, 60, 67: input/output control device, 7
0, 77: input/output device, 80: channel control unit,
81: Data buffer, 82: Input/output interface control unit, 83: Counter, 84, 85: Register, 100 to 104, 110, 117, 12
0,127,1031,1032,200~20
5,1101-1103: Signal line.

Claims (1)

[Claims] 1. Count the difference between the number of accepted signals on tag line A sent from the input/output control device and the number of signals sent on tag line B sent to the input/output control device in response to the signal on tag line A. and means for sending a signal to the tag line B when the difference is not zero.