JP2963696B2 - Data transfer control system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a data transfer control system for performing a DMA (Direct Memory Access) transfer with a block-divided data buffer as a transfer source or a transfer destination.
For example, the present invention relates to a technology effective when applied to a data transfer control system for storing received data by serial communication in a data buffer for each frame or block.

(Prior art)

HDLC (High Level Data Link Control)
When information is exchanged bit-serial according to a procedure or the like, an SCI (serial communication interface) controller transmits and receives data in units called frames. The transmitted / received data is entrusted to the processing of the upper processor, but since the transmission and reception of data by the SCI controller and the data processing by the upper processor are usually performed asynchronously, the transmitted / received data is temporarily stored in the data buffer. In such a case, when transferring the data received by the SCI controller to the data buffer in units of blocks such as frames or transferring the data to be transferred from the data buffer to the SCI controller in units of blocks, To reduce the burden and transfer multiple data blocks efficiently, DM
The data chain function supported by the A (direct memory access) controller can be used.

When this data chain function is used, the upper processor forms in advance a data transfer control table on the memory for linking a large number of prepared buffer areas one after another by a descriptor functioning as a pointer. Each of the descriptors constituting the data transfer control table includes a head address of a buffer area that is a data transfer source or a data transfer destination, a head address of a next descriptor to be chained, and the like. For example, when block transfer of received data to a data buffer, the upper processor sets a predetermined chain block transfer mode instructing the operation in the mode register of the DMA controller, and then indicates a buffer area to which the received data is to be transferred first. The start address of the descriptor (current descriptor address), the start address of the descriptor indicating the buffer area next to the last buffer area to which the received data is to be transferred (error descriptor address), and the common size for each buffer area Initialize the buffer length, etc., expressed in bytes, in a predetermined register inside the DMA controller. After the initialization is performed in this way, when there is a transfer request from the SCI controller, the DMA controller reads a predetermined descriptor according to the value initially set in the current descriptor address register, and the read descriptor indicates Transfer control of the received data of the SCI controller to the buffer area. When the block data is transferred to the predetermined buffer area in this way, the DMA controller updates the value of the current descriptor address register to the start address of the next chained descriptor held by the previously read descriptor. Then, the buffer area is switched, and the transfer of the next block data is continued.

When the buffer area switching process is performed and the current descriptor address matches the error descriptor address, the DMA controller terminates the data transfer because there is no longer a buffer area for which processing of the received data has already been completed.

As an example of a document describing the data chain type DMA transfer, there is “HD6418OS, NPU Hardware Manual” issued by Hitachi, Ltd., July 1988, pp. 378-400.

[Problems to be solved by the invention]

However, in the conventional method in which a plurality of block data is DMA-transferred, the DMA transfer is performed after reading the head address of the descriptor included in the transfer control table or the memory address of the buffer area specified by the descriptor for each block data. Therefore, there is a problem that it takes time to switch the buffer area. For example, when performing data chain transfer or the like between a communication control device and a data buffer, if the overhead for switching the buffer area is large, the communication speed is thereby limited.

In addition, the upper processor performs predetermined processing on the data in the buffer area to which the data has been transferred, but in order to enable DMA transfer to the processed buffer area again, the upper processor must respond to the processing state of the data buffer. Therefore, the error descriptor address and the like must be reset in the DMA controller, and the control for that becomes complicated.

An object of the present invention is to provide a DMA for a plurality of block data.
An object of the present invention is to provide a data transfer control system capable of improving transfer efficiency. Another object of the present invention is to provide a data transfer control which can reduce a load on a processor and simplify a control procedure when performing DMA transfer of a plurality of block data to a block-divided data buffer. It is to provide a system.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, the holding area of the block status corresponding to each block of the data buffer divided into blocks is
Both the DMA controller and the processor are prepared to be readable and writable, and when the block status read by the DMA controller is in the first state, the DMA controller permits the DMA transfer to the block corresponding to the block status, and Causing the DMA controller to change the block status corresponding to the data-transferred block to the second state, and until the data of the block is processed by the processor and the block status changes to the first state again; Is to prohibit data transfer to a block corresponding to.

At this time, when the read block status is in the second state, the processor processes the data of the block corresponding to the block status, and changes the block status corresponding to the processed block to the first state. I do.

In order to facilitate the management of the block status and the control of access to the data buffer by both the DAM controller and the processor, it is preferable to include the holding area of the block status in the definition area of the corresponding block.

In addition, the block definition area is formed in the data transfer control table in the order of the continuously chained blocks,
At this time, the processor initializes the start address of the data buffer, the block length and the number of blocks common to each block, and the start address of the transfer control table in the DMA controller, and sets the DM according to the initialized conditions.
The A controller performs the DMA transfer by sequentially designating the blocks of the data buffer to be chained.

At this time, to increase the efficiency of using the data buffer,
What is necessary is just to specify and use the data buffer blocks in order so as to be linked in a loop.

Then, in order to increase the access speed of the transfer control table by the DMA controller, a DMA controller incorporating the transfer control table can be used. Further, when the DMA controller transfers data to a predetermined block, if the DMA controller sets the start address of the block and the number of data transfer words in the block definition area, the processor can control the start of each block. This eliminates the need to define the address in the definition area in advance.

(Operation)

According to the above-described means, the block status shared by the DMA controller that transfers data to the data buffer and the processor that processes the data transferred to the data buffer is such that the data transfer process and the data process for one block are different. Acting to arbitrate each other so that they occur alternately, which simplifies control by the DMA controller for transfer continuity while preventing undesired destruction of data transferred block data. .
In other words, in the repetition of the data transfer to the data buffer by the DMA controller and the processing of the processor for the data transferred to the data buffer, the processor does not need to reset the data transfer control condition for the DMA controller.

In addition, information for sequentially linking the blocks and the block definition area of the data buffer is initially set in the DMA controller, and based on the initially set information.
Performing DMA transfer by designating the DMA controller itself to chain the blocks of the data buffer in order is
In order to obtain the information indicating the location of the next block to be chained when switching blocks, information indicating the location of the next descriptor and the memory address included in the descriptor specified by the information are conventionally used. It works so as not to require a process of reading data in a plurality of times, thereby achieving high-speed processing for switching blocks of the data buffer.

Then, even when the transfer direction is reversed, the same operation as described above is performed.

〔Example〕

FIG. 1 shows an example of a block diagram of a data transfer control system according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a communication controller, which includes an SCI controller 2, a DMA controller 3, and the like, and includes a main memory 4 and a host processor 5 which are a RAM (random access memory) for storing transmission / reception data and various parameters. Interface with the upper layer via the system bus 6, and performs processing according to a predetermined communication protocol on information transmitted and received through the communication lines TL and RL. Although not particularly limited, the communication controller 1 is formed on one semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique.

The SCI controller 2 includes, but is not limited to, a line control unit connected to another station via the transmission line TL and the reception circuit RL, and a control unit for protocol processing necessary for data transmission and reception by the line control unit. And a buffer for temporarily storing data to be transmitted and received in a first-in first-out format. The SCI controller 2 internally processes a frame input from the line control unit and a command given from the host processor 5, and performs bit serial transmission / reception control processing. For example, a response frame is generated for an input frame, and a response status is generated for a command. In processing for an input frame, the type of the frame is decoded to separate fields, processing corresponding to the type of the frame is given to the built-in control unit, or data of the information field is sequentially stored in a built-in buffer. A response frame is generated for the result of this processing. The command given from the upper layer is a transmission start command or the like, and the built-in control unit generates a response status according to the processing result of executing the command, and returns this to the upper layer.

The DMA controller 3 receives a signal from the SCI controller 2
In accordance with the DMA transfer request, the SCI controller 2 controls the transfer of the data received directly to a predetermined area of the main memory 4 and the transfer control of the data to be transmitted stored in the predetermined area of the main memory 4 directly to the SCI controller 2. Or

The received data transferred to the main memory 4 is subjected to data processing by the host processor 5, and data to be transmitted is generated through data processing by the host processor 5. Of the main memory 4
The above transmission / reception data is also stored as block data distinguished for each frame.

In order to store the transmission / reception data in the main memory 4 while distinguishing the data in units of frames, the main memory 4 has a data buffer 10 divided into blocks. Although not particularly limited, the data buffer 10 is divided into first to n-th blocks BLK1 to BLKn, which are divided into n blocks. Each block has the same block length, and the data buffer 10 is arranged in a continuous address space. For example, a transfer control table 11 is formed in the main memory 4 as an area for defining each of the blocks BLK1 to BLKn. The transfer control table 11 stores the first block BL
First descriptor DCRP1 corresponding to each of K1 to n-th block BLKn
Each of the descriptors includes an area for holding a block status, a block head address, and the number of words to be transferred, one byte at a time. Those descriptors
DCRP1 to DCRPn are arranged in a continuous address space.

The block start address means a start address of a block corresponding to a descriptor including the block start address. For example, the block start address written in the first descriptor DCRP1 is the start address of the first block. The transfer word number indicates the number of bytes of the block data stored in the block corresponding to the descriptor including the transfer word. For example, the number of transfer words written in the first descriptor DCRP1 is the number of bytes of the block data stored in the first block BLK1.

The block status is not particularly limited, but its status 0 is regarded as a status permitting data writing to the corresponding block, and its status 1 is regarded as a status allowing data reading from the corresponding block. The block status defined in this way depends on whether the data buffer 10 is a transfer source or a transfer destination in the DMA transfer, in other words, the received data is written to the data buffer 10 or the data to be transmitted is written. Depending on whether the DMA controller 3 or the host processor 5 has a specific meaning.

That is, when the data received by the SCI controller 2 is block-transferred to the data buffer 10 by the DMA controller 3, the block status for the DMA controller 3 is the DM status of the block corresponding to the description including the block status.
The status is regarded as a status indicating whether or not the A transfer is possible, and is not particularly limited. When the block status is the state 0, the DMA transfer to the corresponding block is permitted, and when the block status is the state 1, the DMA transfer to the corresponding block is prohibited. At this time, for the host processor 5, the block status is regarded as a status indicating whether or not processing can be performed on the block corresponding to the descriptor including the block status. When the block status is the state 1, the data of the corresponding block is read and processed. In the state 0, it means that reading and processing the data of the corresponding block is prohibited.

On the other hand, when the host processor 5 writes data to be transmitted to the data buffer 10 and the DMA controller 3 performs block transfer of the written data to the SCI controller 2, the block status for the host processor 5 is a descriptor including the block status. The status is regarded as a status indicating whether data can be written to a block corresponding to... When the block status is state 0, data writing to the corresponding block is permitted, and when the block status is state 1, data writing to the corresponding block is prohibited. have. At this time, for the DMA controller 3, the block status is regarded as a status indicating whether or not DMA transfer using the block corresponding to the descriptor including the block is possible, and when the block status is state 1, the data of the corresponding block is DMA-transferred. Means to
When the state is 0, the DM for the data of the corresponding block
A means that transfer is prohibited.

When such a definition is given for the block status, the DMA controller 3 and the host processor 5
Although not particularly limited, the following processing is performed with reference to the block status.

When the data received by the SCI controller 2 is block-transferred to the data buffer 10 by the DMA controller 3, as shown in FIG.
The block status included in the predetermined descriptor is read (), and if this is state 0, the received data is transferred to the block corresponding to the descriptor (), and then the block status of the descriptor is rewritten to state 1 and Then, the block start address and the number of words to be transferred are written in the descriptor (). If the block status is state 1, the DMA controller 3 keeps the block status until it is inverted to state 0, in other words, until the data of the block corresponding to the block status is processed by the host processor 5. Pause data transfer to.
On the other hand, when the data transfer by the DMA controller 3 is not performed, the host processor 5 reads the block status included in the predetermined descriptor (). The head address and the number of words to be transferred are read (), and the received data of the corresponding block is read and processed using the read address (), and then the block status of the descriptor is rewritten to state 0 (). If the block status is state 0, the host processor 5 transfers data to such a block until it is inverted to state 1, in other words, until the received data is DMA-transferred to the block corresponding to the block status. Do not process.

When the host processor 5 writes data to be transmitted to the data buffer 10 and the DMA controller 3 performs block transfer of the written data to the SCI controller 2, as shown in FIG.
The block status included in the predetermined descriptor is read (), and if the status is 0, the data to be transmitted is written to the block corresponding to the descriptor (), and then the block status of the descriptor is rewritten to status 1. At the same time, the block start address and the number of words to be transferred are written in the descriptor (). If the block status is state 1, the host processor 5 keeps changing until the block status is inverted to state 0, in other words, until the data of the block corresponding to the block status is transferred to the SCI controller 2 by the DMA controller 3. The writing of data to such a block is suspended. On the other hand, when data is not being written by the host processor 5, the DMA controller 3 reads the block status included in the predetermined descriptor (), and if this is state 1, the block status is included in the descriptor. The block head address and the number of words to be transferred are read (), and the data of the corresponding block is DMA-transferred to the SCI controller 2 using these (),
Thereafter, the block status of the descriptor is rewritten to state 0 (). If the block status is state 0, the DMA controller 3 waits until it is inverted to state 1, in other words, until data to be transmitted is written to the block corresponding to the block status.
Does not perform the DMA transfer processing to such a block.

FIG. 3 shows an example of the DMA controller 3. The DMA controller 3 stores the transfer control table 1
As a register set used for DMA transfer control of block data using the data buffer 1 or the data buffer 10, for example, various registers described below are provided. In FIG. 3, reference numeral 20 denotes a mode register, which is an operation mode in which data received by the SCI controller 2 is DMA-transferred to the data buffer 10 and data to be transmitted written by the host processor 5 in the data buffer 10 is DMA-transferred to the SCI controller 2. The operation mode to be performed is set by the host processor 5.
Reference numeral 21 denotes a control register group. Information necessary for designating areas of the data buffer 10 and the transfer control table 11 and for sequentially linking blocks and descriptors contained therein are initialized by the host processor 5. Registers for this purpose include a transfer control table start address register 22, a data buffer start address register 23, a block length register 24, and a block number register 25. The registers included in the control register group 21 are externally supplied with data through a data input / output buffer 35, and the selection of the register at that time is performed by an address signal externally supplied through an address input / output buffer 36. It has become. The data input / output buffer 35 and the address input / output buffer 36 are connected to the host processor 5 and
It is designed to interface with both SCI controllers 2.

Reference numeral 27 denotes a work register group, for example, a block status register 28 for holding a block status read by the DMA controller 3 and a block status to be written in the transfer control table 11, a block head address register 29, and the number of data transfer words for each block in byte units. And a data transfer word count register 30 held by the data buffer 10, and a block count register 31 indicating which block from the first block of the data buffer 10 is currently used. An address for accessing the transfer control table 11 is held in the transfer control table address register 32, and an address for accessing the data buffer 10 is held in the data buffer address register 33.

Registers 22 to 25 included in control register group 21
Is initialized by the host processor 5, the start address of the transfer control table set in the register 22 is transferred internally to the register 32, and the start address of the data buffer initialized in the register 23 is stored in the register 33. Will be transferred. Transfer control table address register 32
When the transfer control table 11 is accessed with the address held by the, the address of the register 32 is incremented by the arithmetic unit 40 to the next memory address. Similarly, when the data buffer 10 is accessed by the address held in the data buffer address register 33, the address of the register 33 is incremented by the arithmetic unit 40 to the next memory address. Then, every time the data buffer 10 is accessed in byte units, the arithmetic register 40 increments or decrements the number of data transfer words by the value of the count register 30. Whether to increment or decrement is determined according to the data transfer mode. That is, in the case of the DMA transfer mode of the received data, the value is incremented, and finally the number of words of the block data transferred to one block is retained. At this time, the number of data transfer words finally held by the register 30 is written to the descriptor corresponding to the block when the DMA transfer for one block is completed. In the case of the DMA transfer mode of transmission data, the number of transfer words read from a predetermined descriptor is sequentially decremented as an initial value. At this time, when the value of the register 30 is cleared to 0, the DMA controller 41
Performs a block switching process. Block switching processing when DMA transfer of received data is performed
It is provided to the DMA controller 41 in conjunction with the detection of the end of the frame of the received data by the SCI controller 2.

In the block switching process, the value of the block number count register 31 at the time when the process is instructed and the set value of the block length register 24 are raised to the power, and the memory address obtained by this multiplies the data buffer address register 33. Is performed by rewriting the value of. When this block switching process is performed, the value of the transfer control table register 32 is also updated to the next memory address, so that the descriptor corresponding to the switched block can be read.

When the head address of a block is written to the data buffer address register 33 while the DMA transfer mode of received data is set, the head address is held in the block head address register 29. The block start address held in the register 29 is written to a predetermined area of a descriptor corresponding to the block when the DMA transfer for the block is completed. The block start address written in the descriptor in this way is used when the host processor 5 reads data of the block corresponding to the descriptor.
On the other hand, when the DMA transfer mode of the transmission data is set, the block start address held by the descriptor corresponding to the block of the data to be transmitted is read into the block start address register 29, and this value is read into the data buffer address register 33. The memory address of the block may be sequentially generated by internal transfer to the data buffer address register 33, but the data is held in the data buffer address register 33 in accordance with the block switching process based on the internal control of the DMA controller 3 as in the DMA transfer operation of the received data. Alternatively, the head address of the block being used may be used.

The DMA transfer control unit 41 monitors whether the value of the block number register 25 and the value of the block number count register 31 match, and when they match, in other words, the DMA transfer using the last block of the data buffer 10 is performed. When the transfer is completed, the transfer control table address register 32 is rewritten with the transfer control table start address held by the register 22, and the data buffer address register is rewritten.
33 is rewritten by the data buffer start address held by the register 23. As a result, the blocks of the data buffer 10 can be used sequentially in a loop. Further, the DMA transfer control unit 41 determines the state of the block status read into the block status register 28 from the descriptor of the transfer control table 11, and determines the determination result and the DMA transfer mode set in the mode register 20. According to the relationship, it is determined whether or not DMA transfer to the block corresponding to the descriptor is permitted.
When the block switching process is performed after the transfer of the block data to the block, the state of the block status in the block status register 28 is inverted, and the block status of the descriptor is rewritten and controlled by the inverted block status.

The DMA transfer request to the DMA controller 3 is not particularly limited, but is given when the DMA request signal DREQ output from the SCI controller 2 is asserted to the DMA control unit 41. When there is a DMA transfer request, the DMA control unit 41
Asserts a bus request signal BREQ to the host processor 5 via the host control unit 42, and in response thereto, the host processor 5 asserts the bus acknowledge signal BACK, so that the DMA controller 3 acquires the bus right. As a result, the DMA controller 41 asserts the DMA acknowledge signal and gives an approval to the DMA transfer request of the SCI controller 2. Although not particularly limited, the DMA control unit 41 starts the control necessary for the DMA transfer of the block data after giving this approval. The host control unit 42 supplies an interrupt signal IRQ and a DMA transfer end signal DEND to the host processor 5 as necessary.

Next, the DMA of the received data in the system of the above embodiment
An example of the transfer operation will be described mainly with reference to FIG.

The host processor 5 initializes the transfer control table start address, data buffer start address, block length, and number of blocks in the registers 22 to 25 (ST
1) Then, by setting the DMA transfer mode of the received data in the mode register 20 (ST2), the DMA controller 3 can transfer the data received by the SCI controller 2 to the data buffer 10 by DMA. By the processing of the host processor 5 and the DMA controller 3 up to now, for example, the i-th block BLKi and the j-th block BL of the data buffer 10
It is assumed that unprocessed received data remains in Kj. In this state, when a DMA transfer request is issued from the SCI controller 2 to the DMA controller 3 (ST3), the DMA controller 3 requests a bus right from the host processor 5 (ST4). (ST5), an approval of the DMA transfer request is given to the SCI controller 2 (ST6). Then, the DMA controller 3 reads the block status BSTk into the block status register 28 using the start address of the k-th descriptor DCR1Pk held in the transfer control table address register 32 at that time (ST7). The state of the read block status BSTk is determined by the DMA control unit 41. If the state is 0, the block status BSTk is read using the head address of the k-th block BLKk held in the data buffer address register 33 at that time. , The block
The received data from the SCI controller 2 is sequentially transferred to the BLKk by DMA.
Transferred (ST8). When the end of the frame of the received data is detected by the SCI controller 2, the corresponding block BLKk
Is stopped at a predetermined timing. As a result, the DMA control unit 41 inverts the block status BSTk held by the block status register 28 to state 1, and
In addition to rewriting the block status holding area of the descriptor DCRPk, the description of the head address of the block BLKk held at that time in the block head address register 29 and the number of transfer words held by the data transfer word number count register 30 at that time are described. Write to the second and third bytes of child DCRPk (ST9). This allows the host processor 5 to process the received data stored in the block BLKk. And DMA controller 3
Asserts the signal DEND and negates the signal BREQ (ST10), and notifies the host processor 5 of the completion of the transfer of the received data and the relinquishment of the bus right.

As a result, the host processor 5 that has acquired the bus right (ST11) reads the block status BSTi from the i-th descriptor DCRPi to continue the processing of the received data according to the internal operation control procedure (ST12). When detecting that the block status BSTi is state 1, the block head address and the number of words to be transferred are subsequently read from the descriptor DCRPi (ST13), and stored in the corresponding i-th block BLKi based on this. The received received data is read and predetermined data processing is performed (ST14). Thereafter, the block status BSTi of the descriptor DCRPi is rewritten to state 0 (ST15), and storage of new received data in the block BLKi is permitted. According to the above embodiment, the following effects can be obtained.

(1) A block status holding area corresponding to each of the blocks BLK1 to BKLn of the divided data buffer 10 is provided so that both the DMA controller 3 and the host processor 5 can read / write data. When the block status status 0 is
The DMA controller 3 permits the DMA transfer to the block corresponding to the block status, and causes the DMA controller 3 to change the block status corresponding to the data-transferred block to the state 1. Until the block status is processed and the block status is changed to the state 0 again, data transfer to a block corresponding to the block status is prohibited. At this time, when the read block status is state 1, the host processor 5 processes the data of the block corresponding to the block status, and changes the setting of the block status corresponding to the processed block to state 0. Thus, each block BLK1
To BLKn, block statuses BST1 to BSTn corresponding one-to-one
Acts to arbitrate each other so that data transfer processing and data processing for one block are performed alternately, thereby preventing unwanted destruction of data-transferred block data. The control for the transfer continuation by the DMA controller 3 can be simplified. In other words, in the repetition of the data transfer to the data buffer 10 by the DMA controller 3 and the processing of the host processor 5 for the data transferred to the data buffer 10, the host processor 5 resets the data transfer control condition for the DMA controller 3. Need not be required.

(2) The block status is regarded as a status permitting data writing to the corresponding block based on the state 0, and as a status permitting data reading from the corresponding block based on the state 1.
If the meaning of the block status is defined in the host processor 5 and the DMA controller 3, the data buffer 10 becomes a transfer source or a transfer destination in the DMA transfer, in other words, the data buffer 10.
The DMA controller 3 and the host processor 5 determine the meaning of the block status based on whether the received data is written in the block or the data to be transmitted. Therefore, the block status is also used for the process in which the host processor 5 writes the data to be transmitted to the data buffer 10 and the process in which the DMA controller 3 transfers the written data to the SCI controller 2 by DMA. The processes can be arbitrated so that the processes for one block are performed alternately.

(3) By including the holding area of the block status in the definition area of the corresponding block, that is, the descriptor, both the DMA controller 3 and the host processor 5 can easily manage the block status and control access to the data buffer 10. Can be

(4) The block definition areas, that is, the descriptors DCRP1 to DCRPn are formed in the data transfer control table 11 in the order of the continuously chained blocks BLK1 to BLKn. At this time, the host processor 5 The block length and number of blocks common to each block and the number of blocks, and the start address of the transfer control table 11 are initially set in the DMA controller 3, and the DMA controller 3 sets the data buffer 10 in accordance with the initially set conditions.
In order to obtain information indicating the location of the next block to be chained when switching blocks by specifying DMA transfer in order so that blocks are chained, the following description There is no need to read the information indicating the location of the child or the memory address included in the descriptor specified by the information from the transfer control table in a plurality of times, thereby increasing the speed of the process of switching the blocks of the data buffer 10. Can be achieved.

(5) In the operation and effect (4), the DMA controller 3 specifies and uses the data buffers 10 in order so as to be chained in a loop, so that the use efficiency of the data buffers 10 can be increased.

(6) By the above respective effects, the DMA transfer efficiency for a plurality of block data can be improved, and the load on the host processor 5 can be reduced.
Thereby, the throughput of the system can be improved.

(7) By incorporating the transfer control table 11 in the DMA controller 3, the access speed of the transfer control table 11 by the DMA controller 3 can be increased.

(8) When the DMA controller 3 transfers data to a predetermined block, the DMA controller 3 writes the head address of the block and the number of data transfer words in a descriptor corresponding to the block, The host processor 5 does not have to define the start address of each block in each descriptor in advance.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited thereto, and various modifications can be made without departing from the gist of the invention.

For example, in the above embodiment, a case has been described in which block data is DMA-transferred between the data buffer and the SCI controller. However, the present invention is not limited to this, and can be applied to DMA transfer between memories. Further, the configuration of various registers inside the DMA controller is not limited to the above embodiment, and can be changed as appropriate. When the transfer control table is built in the DMA controller, the table may be accessible from inside and outside.
The DMA controller and the input / output circuit such as the SCI controller can be configured by separate chips.

In the above description, the case where the invention made by the present inventor is mainly applied to a system including a communication controller which is a field of use as the background has been described, but the present invention is not limited to this, and It can be widely used in other systems such as a system including a floppy disk controller and a hard disk controller. The present invention can be applied to at least a condition for performing DMA transfer of block data.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

In other words, a specific status is given to the block status that is shared between the DMA controller and the processor in a readable / writable manner according to the data transfer direction and the DMA transfer mode. The block status is determined in light of the definition, necessary processing is performed on the block data, and after the processing is completed, the state of the block status corresponding to the processing target block is reversed. At the time of processing of the DMA controller and the processor for the DMA transfer using the divided data buffer as a transfer source or a transfer destination, by referring to the block status, processing from both sides for one block is performed alternately. The effect that each process can be arbitrated easily That.

Therefore, it is possible to prevent the block data in the data buffer from being undesirably rewritten before the processing is performed on the data, thereby simplifying the control for continuing the transfer by the DMA controller. In other words, in the case where the data transfer to the data buffer by the DMA controller and the processing of the processor for the data transferred to the data buffer are repeated, the processor does not need to reset the data transfer control conditions for the DMA controller. become.

In addition, by including the holding area of the block status in the definition area of the corresponding block, it is possible to facilitate the management of the block status and the control of the access to the data buffer by both the DMA controller and the host processor. is there.

Further, the block definition area is formed in the transfer control table in the order of the blocks that are continuously chained. At this time, the processor determines the start address of the data buffer, the block length and the number of blocks common to each block, and the transfer control table. Block switching is performed by initially setting the start address of the table in the DMA controller and instructing the DMA controller to perform DMA transfer in order to chain the data buffer blocks according to the initially set conditions. In order to obtain the information indicating the location of the next block to be chained, the information indicating the location of the next descriptor and the memory address included in the descriptor specified by the information are obtained multiple times as in the past. Separate reading from the transfer control table is no longer necessary. There is an effect that it is possible to achieve a high-speed block switching process fa.

At this time, there is an effect that the use efficiency of the data buffer can be enhanced by sequentially specifying and using the data buffer so that the DMA buffer is chained in a loop.

According to each of the above effects, the DMA transfer efficiency for a plurality of block data can be improved, and the load on the processor can be reduced, whereby the system throughput can be improved.

By incorporating the transfer control table in the DMA controller, the access speed of the transfer control table by the DMA controller can be increased, and when the DMA controller transfers data to a predetermined block,
By causing the DMA controller to write the head address of the block and the number of data transfer words in the descriptor corresponding to the block, the processor pre-defines the head address of each block in each descriptor. You don't have to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a data transfer control system according to the present invention in relation to DMA transfer of received data. FIG. 2 is a block diagram showing one embodiment of a data transfer control system according to the present invention. FIG. 3 is a block diagram showing an example of a DMA controller included in the systems of FIGS. 1 and 2, and FIG. 4 is a DMA transfer process of received data by the DMA controller. FIG. 7 is an exemplary operation explanatory view showing a relationship between the host data and processing of received data by a host processor. 1 ... Communication controller, 2 ... SCI controller, 3
... DMA controller, 4 ... main memory, 5 ... host processor, 6 ... system bus, 10 ... data buffer, BLK1 to BLKn ... block, 11 ... transfer control table, DCRP1 to DCRPn ... descriptor , 20 ... mode register, 22 ... transfer control table start address register, 23
…… Data buffer start address register, 24 …… Block length register, 25 …… Block number register, 28 …… Block status register, 29 …… Block start address register, 30 …… Data transfer word count register
31: Block number count register, 32: Transfer control table address register, 33: Data buffer address register, 41: DMA control unit.

Continuation of the front page (72) Inventor Nobuyoshi Furuhata 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer Engineering Co., Ltd. (56) References JP-A-63-292261 (JP, A) 63-124161 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 13/28 310

Claims (3)

(57) [Claims] 1. A processor comprising: a processor; a DMA controller; and a memory accessible by both the processor and the DMA controller. The memory includes a data buffer composed of a plurality of blocks, and a descriptor area for each block. A transfer control table to be formed, each of the descriptor areas has a block status holding area and a block definition area, and the processor has a DMA controller provide a DMA controller with a head address of the data buffer and the transfer control. The start address of the table and the size and number of the blocks can be initialized, and the DMA controller responding to the DMA transfer request can perform the DMA transfer control in which the blocks are sequentially specified in accordance with the initial settings by the processor. The block status read from the descriptor area is in the first state When DMA transfer is performed on the block corresponding to the block status, the block status of the block subjected to the DMA transfer is changed to the second state,
The processor permits processing of the data of the block and suppresses new data transfer to the block until the processing returns to the first state by the processor after the processing is completed. Data transfer control system. 2. The data transfer control system according to claim 1, wherein said DMA controller is capable of sequentially specifying blocks so as to be chained in a loop in DMA transfer control in which blocks are sequentially specified. 3. The method according to claim 1, wherein the DMA controller is configured to, when data is transferred to the block, perform processing for setting a head address of the block and the number of data transfer words in a block definition area of the block. 3. The data transfer control system according to claim 2, wherein: