JP3110024B2 - Memory control system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a memory control device, and more particularly to a memory control device that centrally manages memory accesses.

2. Description of the Related Art Generally, in a tightly coupled multiprocessor system in which a plurality of processing devices share a storage device and operate, a bus system is used as a mechanism for arbitrating memory access from each processing device. There is a case where a device for management is placed in the system.

Of these, the bus system is often used in relatively small devices, and has the feature that the configuration is simple and the amount of hardware is small.

On the other hand, a device that centrally manages memory access is called a memory control device or a system control device. The device is located at the center of the system and has a one-to-one path with all processing devices in the system. A memory access request from the device can be simultaneously received and processed.
The processing result is returned to the request source device as a reply.
This method requires a larger amount of hardware than the bus method, but is superior in processing performance, and is therefore often used in high-performance computers.

On the other hand, in the tightly-coupled multiprocessor system, the processing devices execute processing while communicating with each other. Such communication is called inter-processor communication. In a system having a memory control device, in most cases, the memory control device acts as an intermediary, and for this purpose, a communication path between each processing device and a communication reception / control unit is provided.
Each processing device sends inter-processor communication to the memory control device using a normal memory access path, and is delivered from the memory control device to a destination processing device via a dedicated communication path. When sending a communication from the memory control device to the destination processing device, a method of sending the communication only to the destination processing device or a method of sending the communication to all the subordinate processing devices at once and receiving each device to receive the communication addressed to itself. There is a way to accept only.

Nowadays, the main storage capacity of a computer has become relatively inadequate with the improvement of the capacity of the information processing apparatus and the dramatic increase in the amount of processing data. Therefore, if the main memory area becomes insufficient during processing, data that is not used for the time being is expelled to the secondary storage device, and thereafter, the necessary data is read from the secondary storage device and processing is continued. There is a method of doing. However, a magnetic disk device often used as a secondary storage device has a read / write speed that is two to three digits slower than that of a main storage device. Therefore, an increase in access to the secondary storage device directly appears as a reduction in processing speed.

On the other hand, a high-speed memory element used in a main storage device of a high-performance computer is expensive, and it is not easy to mount a main memory having a necessary and sufficient capacity due to economic restrictions.

In order to fill a gap between a high-speed main memory and a low-speed magnetic disk, a large-capacity semiconductor memory device using a relatively inexpensive and low-speed semiconductor memory element has been developed. This semiconductor storage device is called an electronic disk or a disk cache, and is a device that looks exactly the same as a magnetic disk except for the speed from a processing device, and an extended storage device, which is a memory control device similar to the main storage device. Some devices are directly connected to the device and managed by software.

Of these two types of semiconductor storage devices, the former, that is, those having an interface equivalent to a magnetic disk, may be managed in the same manner as a conventional disk, and there is no particular control problem.

On the other hand, since the access time of the extended storage device is about several times that of the main storage device, if data on the extended storage is accessed in the same manner as the main storage device, the processing performance of the system is greatly reduced. To avoid this, a method is generally adopted in which the required amount of data is transferred from the extended storage to the main storage all at once and then used, thereby increasing the storage capacity of the main storage. The same effect as the above can be obtained.

Conversely, unnecessary data on the main memory that may be used in the future is saved from the main memory to the extended memory. Such data transfer between the main storage and the extended storage is usually performed by the data transfer means in the memory control device without burdening the instruction processing device or the input / output processing device.

The data transfer request by the data transfer means described above is generated by executing a data transfer instruction. The data transfer commands are roughly classified into two types. One of them is called a synchronous transfer instruction, which is directly executed by the instruction processing device and has execution of the next instruction until the transfer is completed. The other is called an asynchronous transfer instruction, and the input / output processing device performs processing according to an instruction from the instruction processing device, and the instruction processing device can execute another task until the transfer is completed.

That is, in the case of a synchronous transfer instruction, the instruction processing device
In the case of an asynchronous transfer instruction, a data transfer request is issued from the input / output processing device to the memory control device.

The above-described data transfer request starts the transfer by designating the start address of the main storage device, the start address of the extended storage device, the transfer data amount, and the transfer direction. As described above, since the data transfer request has a lot of attached information, the data transfer request is sent to the memory control device in a plurality of times.

The transfer data amount is usually about several kilobytes, and the time required for the transfer is about several hundred to several thousand steps in terms of the number of instruction steps. As described above, the processing time of the data transfer request is much longer than that of other various processing requests to the memory control device such as a memory access request.

In addition, since many hardware such as the main storage device, the extended storage device, and the data transfer means are involved, if a failure occurs during the transfer, the location of the failure, the notification of the failure content, and the subsequent processing method are complicated. Becomes

When a processing request such as the above data transfer request or another normal memory access request is issued from the instruction processing device or the input / output processing device to the memory control device, a reply is sent to the requesting device at the end of the processing. Is returned. The reply includes a processing result including data read from the main storage device, failure notification information when a failure occurs with the processing, and the like. That is, in the conventional memory control device, the data transfer request between the storage devices is also treated as one of various processing requests in the same row, so that the reply to the data transfer request is not returned to the request source device until all the data transfer is completed. . Therefore, there is a drawback that the request source device in the reply waiting state is prevented from executing other processes.

In addition, since it cannot be determined whether the data transfer time is long or the reply is not transmitted due to the occurrence of a failure, it is difficult to detect the failure early by monitoring the elapsed time from the issuance of the processing request to the receipt of the reply.

Furthermore, in order to send necessary information when a failure occurs during data transfer, the interface of reply information is increased in advance, or a function is provided for the request source device to read the failure status from the memory control device. There was also a disadvantage that it had to be kept.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a memory control system in which a processor can perform other processing during data transfer processing.

A memory control system according to the present invention includes a host device, a memory device, and a data transfer between the host device and the memory device in response to a data transfer request from the host device. A memory controller for controlling data transfer, the memory controller comprising: means for sending a reply in response to receiving a data transfer request from the higher-level device; and Means for sending an end signal indicating the end of the transfer in response to the end of the transfer, wherein the higher-level device includes means for executing the following processing after receiving the reply and before receiving the end signal. It is characterized by.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of a memory control system according to the present invention. In the figure,
A memory control system according to an embodiment of the present invention includes a memory control device 10, a main storage device 16, an extended storage device 17, and a processor (not shown) having an instruction processing device and an input / output processing device. I have.

A request reception port 11 for receiving a request signal from a processor, a reply transmission unit 12 for transmitting a processor helicopter, an inter-processor communication transmission unit 13 for transmitting a communication signal to the processor, and a main memory in the memory control device 10. A main memory access control unit 14 for controlling access to the device 16;
And a data transfer control unit 15 that controls data transfer between the storage device 17 and the extended storage device 17.

In the figure, a is a processing request signal from the instruction processing device, b is a processing request signal from the input / output processing device, c is a reply signal to the instruction processing device, d is a reply signal to the input / output processing device, e Is an inter-processor communication signal to the instruction processing device, and f is an inter-processor communication signal to the input / output processing device.

In addition, g is an operation instruction signal to the main memory access control unit 14, h is a reply instruction signal from the main memory access control unit 14, j is an operation instruction signal to the data transfer control unit, and k is an inter-processor communication transmission unit. , L is a reply instruction signal from the inter-processor communication sending unit, and m is a processing request signal from the data transfer control unit 15.

Further, n is a reply from the reply sending unit 12 to the data transfer control unit, p is a processing request signal to the main storage device 16, q is a reply signal from the main storage device 16, and r is a processing signal to the extended storage device 17. The request signal s is a reply signal from the extended storage device 17.

In such a configuration, first, an operation when a normal memory access request is issued from the request source device to the memory control device will be described. When a request signal a from the instruction processing device or a request signal b from the input / output processing device is input to the request reception port 11, the request reception port 11 decodes the request, and the request is a memory access request. An operation instruction signal g is sent to.

Upon receiving this, the main memory access control unit 14
A processing request signal p is issued to the P. 16. On the other hand, the reply signal q from the main storage device 16 passes through the main memory access control unit 14 and the reply sending unit 12 and the reply signal c or d.
Is returned to the requesting device.

Next, the operation in the case where the inter-processor communication request is issued from the request source device to the memory control device will be described. When a request signal a from the instruction processing device or a request signal b from the input / output processing device is input to the request reception port 11,
The request receiving port 11 decodes this, and sends an operation instruction signal k to the inter-processor communication sending section 13 because it is a request for inter-processor communication. Upon receiving this, the inter-processor communication sending unit 13 sends the inter-processor communication signals e and f to all connected devices, that is, the instruction processing device and the input / output processing device, and then sends a reply instruction signal to the reply sending unit 12. Send l. Upon receiving this, the reply sending unit 12 sends a reply signal c or d to the requesting device.

Also, the processing request sent from the request source device is stored in the main storage device.
If the request is a data transfer request between the storage device 16 and the expansion storage device 17, the request reception port 11 sends a data transfer operation instruction signal j to the data transfer control unit 15. At the same time, a reply instruction signal (not shown) is sent from the request receiving port 11 to the reply sending unit 12, and a reply signal indicating that the data transfer start request has been normally received is returned to the request source device. It is.

Data transfer control unit receiving data transfer operation instruction signal j
15 is a processing request signal m for memory access to the request reception port 11 when accessing the main storage device 16.
And sends a reply n to the reply sending unit 12
Receive from In this case, the memory access operation itself is performed via the main memory access control unit 14, as in the case of access from a processing device outside the memory control device 10.

On the other hand, when the data transfer control unit 15 accesses the extended storage device 17, the processing request signal r is directly sent to the extended storage device 17.
And a reply signal s is received. Then, when all the requested data transfers are completed, the data transfer control unit 15 notifies the inter-processor communication request by the processing request signal m to the request receiving port 11. The request receiving port 11 which has received the inter-processor communication request sends an operation instruction signal k to the inter-processor communication sending unit 13 to the inter-processor communication control unit 13 to notify the end of the requested data transfer to the request source device. A communication signal e or f to inform is sent.

Here, the operation instruction signal k includes an end status indicating whether or not the data transfer has ended normally. Accordingly, the processor receives the communication, and the requesting device can determine whether the requested data transfer has been completed normally, and if not, it can know detailed information of the error. . As a result, the processor can perform predetermined failure processing.

Effect of the Invention As described above, the present invention responds to a data transfer request between the main memory and the extended storage, which has a different characteristic from a general memory access or other processing request and takes a long processing time, in response to the request reception. The reply is immediately returned, and the notification of the transfer end is controlled by the transfer end communication by the inter-processor communication, so that the reply waiting time of the request source device does not increase, and the request source device performs the data transfer during the data transfer. It is possible to send the end status information of data transfer as communication data of inter-processor communication without affecting other processing and the time monitoring timer, so that detailed information can be sent when a transfer failure occurs. There is an effect that no special means is required.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory control system according to an embodiment of the present invention. Explanation of Signs of Main Parts 11 Request Request Port 12 Reply Sending Unit 13 Inter-Processor Communication Sending Unit 14 Main Memory Access Control Unit 15 Data Transfer Control Unit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/00 G06F 15/16

Claims (1)

(57) [Claims] 1. A memory control system comprising: a host device; a memory device; and a memory control device that controls data transfer between the memory devices in response to a data transfer request from the host device. The memory control device transmits a reply in response to receiving the data transfer request from the host device, and responds to the end of the requested data transfer by sending an end signal indicating the end of the data transfer request. Means for transmitting the data as data, and wherein the higher-level device includes means for performing the following processing after receiving the reply and before receiving the end signal.