JPH02291039A - Memory control system - Google Patents

Abstract

PURPOSE:To efficiently execute processing by sending reply from a memory controller with responding to the reception of a data transfer request from a host device and executing the next processing after the reply is received in the host device. CONSTITUTION:For example, when a normal memory access request is issued from a request source device to a memory controller 10 and a request signal (a) is inputted from an instruction processor or a request signal (b) is inputted from an input output processor to a request reception port 11, the request reception port 11 decodes this signal and sends an operation instruction signal (g) to a main memory access control part 14. The main memory access control part 14 receiving this signal issues a processing request signal (p) to a main storage device 16. To the signal (p), a reply signal (q) from the main storage device 16 is passed through the main memory access control part 14 and a reply sending part 12 and returned to the request source device as reply signals (c) and (d). The request source device discriminates whether requested data transfer is normally finished or not. Then, the next processing is executed.

Description

TECHNICAL FIELD The present invention relates to a memory control device, and more particularly to a memory control device that centrally manages memory access.

BACKGROUND TECHNOLOGY In general, in tightly coupled multiprocessor systems in which multiple processing units operate by sharing a storage device, a bus method is used as a mechanism for arbitrating memory access from each processing unit, and a bus method is used as a mechanism to arbitrate memory access from each processing unit. A device for managing may be placed.

Among these, the bus method is often adopted for relatively small devices.
It is characterized by a simple configuration and a small amount of hardware.

On the other hand, a device that centrally manages memory access is called a memory control device or system control device, and is located at the center of the system and has a one-to-one path to all processing devices in the system, and each It is possible to simultaneously accept and process memory access requests from devices. The processing result is returned to the requesting device as a reply. Although this method requires more hardware than the bus method, it has superior processing performance and is therefore often used in high-performance computers.

On the other hand, in a tightly coupled multiprocessor system, each processing device executes processing while communicating with each other. This type of communication is called interprocessor communication. In most systems equipped with a memory control device, the memory control device or the like acts as an intermediary, and for this purpose, communication paths and communication reception/control means are provided between the memory control device and each processing device. Each processing device sends inter-processor communication to the memory control device using a normal memory access path, and from the memory control device it is delivered to the destination processing device through a dedicated communication path. When sending a communication from a memory control device to a destination processing device, there are two methods: sending it only to the destination processing device, and sending it to all subordinate processing devices at the same time, so that each device that receives it sends the communication addressed to itself. There is a method of accepting only

Nowadays, as the capacity of information processing devices increases and the amount of data to be processed increases dramatically, the main memory capacity of computers is becoming relatively insufficient.

Therefore, if the main memory runs out of space during processing, data that will not be used for the time being will be removed to the secondary storage, and then data that will be needed will be read from the secondary storage and processing will continue. There is a method to do so. However, the read/write speed of magnetic disk devices, which are often used as secondary storage devices, is two to three orders of magnitude slower than that of main storage devices. Therefore, an increase in access to the secondary storage device directly manifests itself as a decrease in processing speed.On the other hand, the high-speed memory elements used in the main storage device of high-performance computers are expensive, making it difficult to achieve economical results. Due to constraints, it is not easy to implement main memory with sufficient capacity.

Therefore, in order to bridge the gap between high-speed main memory and low-speed magnetic disks, large-capacity semiconductor storage devices using relatively inexpensive and low-speed semiconductor storage elements have been developed. These semiconductor storage devices include devices called electronic disks and disk caches, devices that look exactly the same as magnetic disks to the processing device except for speed, and devices called expanded storage devices.
Like the main storage device, there is a device that is directly connected to the memory control device and managed by software.

Of these two types of semiconductor storage devices, the former, that is, one having an interface equivalent to a magnetic disk, can be managed in the same manner as a conventional disk, and there are no particular problems in control.

On the other hand, since the access time of the expanded storage device is several times that of the main storage device, if data on the expanded storage device is accessed in the same way as the main storage device, the processing performance of the system will drop significantly. To avoid this, a method is generally adopted in which the required amount of data is transferred from expanded storage to main memory in one go, and then used. By doing so, the storage capacity of main storage is expanded. You can get the same effect as you did.

Conversely, unnecessary data on the main memory that may be used in the future is saved from the main memory to the expanded storage. Such data transfer between the main memory and the extended memory is normally performed by data transfer means within the memory control device without placing a burden on the instruction processing device or the input/output processing device.

A data transfer request by the data transfer means described above is generated by executing a data transfer command. The data transfer commands are broadly classified into two types.

One is called a synchronous transfer instruction, which is directly executed by the instruction processing device, and execution of the next instruction is awaited until the transfer is completed. The other type is called an asynchronous transfer instruction, in which the input/output processing device performs processing according to instructions from the instruction processing device, and the instruction processing device can execute another task until the transfer is completed.

That is, a data transfer request is issued to the memory control device from the instruction processing device in the case of a synchronous transfer instruction, and from the input/output processing device in the case of an asynchronous transfer instruction.

The above data transfer request requires the start address of the main storage device,
The transfer is started by specifying the start address of the extended storage device, the amount of data to be transferred, and the transfer direction. As described above, since the data transfer request includes a lot of information belonging to τj, it is sent to the memory control device in multiple parts.

The amount of data to be transferred is usually on the order of several kilobytes, and the time required for the transfer is equivalent to approximately several hundred to several thousand instruction steps. As described above, the processing time for a data transfer request is extremely long compared to other various processing requests to the memory control device such as a memory access request.

In addition, since a lot of hardware is involved, such as the main storage device, expanded storage device, and data transfer means, if a failure occurs during transfer, it is complicated to identify the failure location, notify the failure details, and process the subsequent processing. becomes.

When an instruction processing unit or input/output processing unit issues a processing request such as the above-mentioned data transfer request or other normal memory access request to the memory control unit, a reply is sent to the requesting device when the processing is completed. is returned. This reply includes processing results such as data read from the main storage device, failure notification information when a failure occurs during processing, and the like. In other words, in conventional memory control devices, data transfer requests between storage devices are treated equally as one of various processing requests, so a reply to a data transfer request is not returned to the requesting device until all data transfers are completed. . Therefore, there is a drawback that the requesting device in the reply waiting state is prevented from executing other processing.

Furthermore, since it is not possible to determine whether the data transfer time is long or whether a reply is not sent due to the occurrence of a failure, it is difficult to detect failures early by monitoring the elapsed time from issuing a processing request to receiving a reply.

Furthermore, in order to send the necessary information when a failure occurs during data transfer, it is necessary to increase the number of reply information interfaces in advance, or provide a function for the requesting device to read the failure status from the memory control unit. It also had the disadvantage of having to be kept.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a memory control system that allows a processor to perform other processing during data transfer processing.

Configuration of the Invention A memory control system according to the present invention includes a host device, a memory device, and data transfer between the host device and the memory device in response to a data transfer request from the host device, and data transfer between the host device and the memory device. and a memory control device that controls data transfer, the memory control device including means for sending a reply in response to receiving a data transfer request from the host device, and the memory control device includes means for sending a reply in response to receiving a data transfer request from the host device. The method is characterized in that it includes means for executing the following process after receiving the reply.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of main parts of an embodiment of a memory control system according to the present invention.

In the figure, a memory control system according to an embodiment of the present invention includes a memory control device 10, a main storage device 16, an expansion storage device 17, and a processor (not shown) having an instruction processing device and an input/output processing device. It is configured.

The memory control device 10 includes a request receiving port 11 that receives request signals from the processor, a reply sending section 12 that sends a reply to the processor, an interprocessor communication sending section 13 that sends a communication signal to the processor, and a main port 11 that receives a request signal from the processor. It is configured to include a main memory access control section 14 that controls access to the storage device 16, and a data transfer control section 15 that controls data transfer between the main storage device 16 and the expanded storage device 17.

In the figure, a is a processing request signal from the instruction processing device, b is a processing request signal from the input/output processing device, C is a reply signal to the instruction processing device, d is a reply signal to the input/output processing device, and e is an inter-processor communication signal to the instruction processing device, and f is an inter-processor communication signal to the input/output processing device.

Further, g is an operation instruction signal to the main memory access control section 14, h is a reply instruction signal from the main memory access control section 14, j is an operation instruction signal to the data transfer control section, and k is an operation instruction signal to the interprocessor communication sending section. Ω is a reply instruction signal from the interprocessor communication sending unit, and m is a processing request signal from the data transfer control unit 15.

Furthermore, n is a reply from the reply sending section 12 to the data transfer control section, p is a processing request signal to the main storage device 16, q is a reply signal from the main storage device 1-6, and r is a reply to the expansion storage device 17. processing request signal, S is the extended storage device 17
This is a reply signal from.

In this configuration, first, the operation when a normal memory access request is issued from the requesting device to the memory control device will be described.

When the request signal a from the instruction processing device or the request signal b from the input/output processing device is input to the request reception port 11, the request reception port 11 decodes it and, since it is a memory access request, sends it to the main memory access control unit. The operation instruction signal g is sent to 14.

Upon receiving this, the main memory access control unit 14 issues a processing request signal p to the main memory device 16.

On the other hand, the reply signal q from the main memory device 16 is returned to the requesting device as a live signal C or d via the main memory access control section 14 and the reply sending section]2.

Next, the operation when an inter-processor communication request is issued from the requesting device to the memory control device will be described.

When a request signal a from an instruction processing device or a request signal b from a human output processing device is input to the request reception button 1.1, the request reception {=I port 1. Since this is a communication request, an operation instruction signal k is sent to the interprocessor communication sending section 1-3.

After receiving this, the inter-processor communication sending section 13 sends the inter-processor communication signals e and f to all the connected devices, that is, the instruction processing device and the input/output processing device, and then sends the reply sending section 12 a reply instruction signal. send g. The reply sending unit 12 that receives this sends a reply signal C or d to the requesting device.

In addition, the processing request sent from the requesting device is processed by the main storage device 1.
6 and the extended storage device 17, the data transfer control unit 15 is sent from the request reception port 11.
A data transfer operation instruction signal j is sent to. At the same time, a reply instruction signal g is sent to the replay sending]2 output unit 12, and a reply signal indicating that the data transfer start request has been successfully received is returned to the requesting device.

Data transfer control unit 1 receiving data transfer operation instruction signal j
5 issues a processing request signal m for memory access to the request receiving poll l.

In this case, the memory access operation itself is performed via the main memory access control unit 14 as in the case of access from a processing device outside the memory control device 10.

On the other hand, when the data transfer control unit 15 accesses the expanded storage device 17, it directly sends a processing request signal r to the expanded storage device 17 and receives a reply signal S. When all the requested data transfers are completed, the data transfer control unit 5 notifies the request receiving port 1 of an inter-processor communication request using a processing request signal m. The request receiving ports 1 and 11 that have received this inter-processor communication request send an operation instruction signal k to the inter-processor communication control unit 13 to transmit the requested data to the requesting device. A communication signal e or f is sent to notify the end.

Here, the operation instruction signal l{ includes an end status indicating whether the data transfer has ended normally. Therefore, when the processor receives the communication, the requesting device can determine whether the requested data transfer has been completed normally, and if it has not been completed normally, it can know detailed information about the error. be. This allows Broceza to perform predetermined fault handling.

Effects of the Invention As explained above, the present invention responds to a request for data transfer between main memory and extended memory, which is different in nature from processing requests such as general memory access and takes a long processing time. By controlling the requesting device to immediately return a reply and notifying the end of the transfer using transfer end communication via inter-processor communication, the requesting device does not have to wait long for a reply. In addition to not affecting other processes or time monitoring timers, it is possible to send data transfer completion status information as communication data for interprocessor communication, so detailed information can be sent in the event of a failure during transfer. This has the effect of not requiring any special means.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a memory control system according to an embodiment of the present invention. Explanation of symbols of main parts 11...Request reception port 1, 12...Reply sending unit 13...Interprocessor communication sending unit 14...
・Main memory access control unit 15...Data transfer control unit

Claims (1)

[Claims] (1) A host device, a memory device, and memory control that controls data transfer between the host device and the memory device and data transfer between the memory devices in response to a data transfer request from the host device. a memory control system having a device, the memory control device including means for sending a reply in response to reception of a data transfer request from the host device, and the host device, after receiving the reply, transmits the next request. A memory control system comprising means for performing processing.