JP2734246B2 - Pipeline bus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus which realizes an extremely high data transfer throughput by performing physical division and shortening a data transfer period limited by a signal propagation delay time.

[0002]

2. Description of the Related Art In a conventional computer system, generally, boards constituting the system are connected via a bus. The wiring length of this bus must be sufficiently shorter than the distance over which the signal propagates during the data transfer cycle, and there is a problem that the data transfer cycle cannot be shortened to a certain extent. This is a problem caused by the physical size of the boards making up the system. In a general system, the wiring length of the bus is required to be about several tens of cm,
The data transfer cycle is set to several tens nS.

When the main memory is shared, the performance of the system greatly depends on the ability to supply data from the main memory, that is, the data transfer throughput of the bus. For example, it has been pointed out that in a bus-coupled multiprocessor system, it is necessary to increase the data transfer throughput of the bus because the bus becomes a bottleneck.

In order to increase the data throughput of the bus,
A pipeline bus has been proposed in which a bus is physically divided and data transfer is performed in a pipeline. By the physical division, not only the wiring length can be shortened, but also the connection relationship, which has been previously unspecified many to unspecified many, becomes one-to-one, so that a termination for suppressing signal reflection can be taken. As a result, the data transfer clock can be increased without being limited by the wiring length, and the data transfer throughput can be further increased. In this case, the distance over which the signal propagates during the data transfer cycle becomes shorter, and in some cases, becomes shorter than the wiring length, so that a plurality of data being transferred exists on the partial bus.

[0005]

Conventionally, in a pipeline bus, control and data transfer relating to bus occupancy are separated, and bus occupation is operated at a low frequency corresponding to the physical size of the bus. When the bus could be occupied, data was being transferred at a higher frequency. This is because the entire bus needs to be secured before data transfer because the positional relationship between a unit that outputs data and a unit that receives data changes. When such occupancy control is performed, the bus can handle only one data transfer, and the data transfer efficiency is reduced, which is an obstacle for increasing the data transfer throughput.

[0006]

In order to avoid a decrease in data transfer efficiency, which has been a problem in the conventional pipeline bus, in the pipeline bus of the present invention, the units constituting the system are physically divided. An occupation line indicating the occupation state of the specified partial bus, a data line, and a state line indicating the result of data transfer are connected to each other, and occupation information on the occupation line, data on the data line, and data transfer result on the state line are transmitted. A scheduler that arbitrates a bus use request from a unit that transfers data in one direction and performs data transfer is provided with an identifier of a unit that uses a partial bus as occupancy information, and the occupancy information provided by the scheduler is provided. Based on the designation, each unit independently outputs data and receives data to indicate the occupation state on the occupation line. To partial bus corresponding to the signal present and performs the occupancy management. This makes it possible for a plurality of independent data being transferred to be present on the ring-shaped bus, thereby increasing the data transfer throughput.

[0007]

Next, the operation of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a pipeline bus of the present invention. In FIG. 1, 100 is a pipeline bus, 1
Is a sending unit, 2 is a receiving unit, 3 is an occupation line, 4 is a data line, 5 is a status line, 8 is a data memory, and 9 is a scheduler.

FIG. 2 is a diagram showing a configuration of a sending unit 1 in the pipeline bus of FIG. 1, FIG. 3 is a diagram showing a configuration of a receiving unit 2 in the pipeline bus of the present invention of FIG. 1, and FIG. FIG. 2 is a diagram showing a configuration of a scheduler 9 in one pipeline bus. 2 to 4,
11 is an address counter, 12 is occupancy check means, 13 is data output means, 14 is data capture means, 15 is status output means, 16 is status check means, 17 is data transfer request means, 18 is data write means, and 19 is data write means. The slot issuance control unit.

In the pipeline bus 100 of the present invention, 1
Following one or more sending units 1, one or more receiving units 2 are connected by occupation lines 3, data lines 4 and status lines 5. Occupation information, data, and state information propagate in one direction on the occupation line 3, the data line 4, and the state line 5.

In consideration of the operation time of the circuit, the data is sent with a delay of the occupation confirmation time with respect to the occupation information, and the state information is sent with a further delay of the state transition time from the data. Each signal continues for a data transfer period, and the bus occupancy control in the pipeline bus 100 is performed on slots which are a set of occupation information, data and state information with a time delay. FIG. 8 is a diagram showing a time relationship between signals constituting a slot.
Apparently, the slot appears to flow on the pipeline bus, and data is transferred by sending and receiving data to the slot at an appropriate timing.

The occupation information specifies the type of the slot, the sending unit having the right to send data to the slot, and the receiving unit to which the data on the slot is to be taken. The status information indicates a result of the data transfer. When the receiving unit normally receives the data, the receiving unit outputs a receiving state as state information.

When performing data transfer, the sending unit 1 first activates the data transfer requesting means 17 and first specifies its own identifier and the identifier of the data transfer destination unit to the scheduler 9 to use the slot. Request.
The scheduler 9 performs arbitration between the slot use requests from the plurality of transmission units 1 and selects one slot use request. Subsequently, the slot issuance control means 19 is activated to issue a data slot in which the request source unit and the data transfer destination unit designated in the use request of the slot are respectively a sending unit and a receiving unit.

The occupancy confirmation means 12 of each unit always
When the occupation line 3 is monitored and a data slot is detected, if the transmission unit is designated, the data output means 13 is activated, and after the occupation confirmation time, the data line 4 is designated by the address counter 11. The data on the external data memory 8 is output. If the receiver is designated as the receiving unit, the data fetching means 14 is activated to fetch the data sent on the data line 4 after the occupation confirmation time, and the data writing means 14 is activated to activate the address counter 11. Then, the data is written to the external data memory 8 by designating the address, the status output means 15 is activated, and the reception status is output to the status line 5 after the status transition time. No data to capture, or
If the writing of the fetched data fails, no acceptance status is output. In order to determine whether or not there is data to be taken in on the data line 4, the simplest method is to add a bit indicating validity to the data on the data line 4.

In the operation of the independent sending unit and the receiving unit, data is always sent first due to physical connection. Data transfer is performed by taking in the previously transmitted data. The occupancy confirmation means 12 of the scheduler 9 also constantly monitors the occupation line 3 and, upon detecting a data slot, activates the state confirmation means 18 and sends it on the state line 5 after a further state transition time from the occupation confirmation time. The received status information is checked to confirm that the data transfer by the data slot has been performed normally. If the data transfer is not performed normally, the scheduler 9 restarts the data transfer.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 5 is a diagram showing one embodiment of the pipeline bus of the present invention. In FIG. 5, reference numeral 200 denotes a pipeline bus of the present embodiment, and 201 denotes a normal bus. 2
Numeral 0 denotes a module corresponding to the sending unit 1, the receiving unit 2, and the data memory 8. Reference numeral 90 denotes an extended scheduler corresponding to the scheduler 9. In the pipeline bus 200 of the present embodiment, the extended scheduler 90 is used as a start point and an end point,
One or more modules 20 are connected by an occupation line 3, a data line 4 and a status line 5 such that the sending unit 1 of each unit is followed by the receiving unit 2 of each module 20.

FIG. 6 is a diagram showing the configuration of the module 20. In FIG. 6, 1 is a sending unit, 2 is a receiving unit, and 8 is a data memory. 11 is an address counter, and 12 is an occupation confirmation means. In this embodiment, an identification number is given to each unit, and
2 compares the identification number of the unit given as the occupation information on the occupation line 3 with its own identification number. 13 is a data output means, 14 is a data fetch means, 15 is a status output means, and 18 is a data writing means. further,
A block data transfer request control unit 21 corresponds to the data transfer request unit 17.

FIG. 7 is a diagram showing the configuration of the extended scheduler 90. In FIG. 7, reference numeral 12 denotes an occupancy check unit, 16 denotes a state check unit, and 19 denotes a slot issue control unit. 91
Is a block data transfer request buffer, 92 is a used unit table, 94 is a population counter, 95
Is a remaining issue number counter, and 96 is an issue interval timer. The extended scheduler 90 controls a plurality of block data transfers at the same time, and has the same number of block data transfers that simultaneously control a set of the remaining issue counter 95 and the issuance interval timer 96.

In order to perform block data transfer using the pipeline bus 200 of this embodiment, the module 20
Is the sending unit of the data transfer source, the receiving unit of the data transfer destination, the head address of the data area to be transferred, the head address of the area where the transferred data is to be stored, and the size of the data to be transferred via the normal bus 201. Is written to the block data transfer request buffer 91 of the extended scheduler 90 to request block data transfer.

Reference numeral 94 denotes a population counter.
The extended scheduler 90 resets the population counter 24 for a fixed period, activates the slot issuing means 19, and increments each time a slot is issued. The usage rate of the pipeline bus 200 can be known from the value of the population counter 24. An upper limit is set for the value of the population counter, and when the value exceeds the upper limit, a new block data transfer is not activated.

When starting a new block data transfer, the extended scheduler 90 first secures one set of a remaining issue number counter 95 and an issue interval timer 96 used for block data transfer. If the set of the remaining issue number counter 95 and the issue interval timer 96 cannot be secured, that is, if the number of block data transfers that can be supported by hardware has already been performed, the block data transfer being executed is completed and the remaining issue number counter It waits until a set of 95 and issue interval timer 96 can be secured.

Remaining issue number counter 95 and issue interval timer 9
When the set of 6 has been secured, the next step is to extend the scheduler 9
0 checks the block data transfer request buffer 91. If there is a request for block data transfer, the block data transfer request having the highest priority is selected. In the present embodiment, the priority is not particularly defined, and is processed in order from the block data transfer request made earlier in time.

Further, the extended scheduler 90 searches the operating unit table 92 to determine whether the source unit and the destination unit of the selected block data transfer request are being used by another data transfer, and
If not used, the block data transfer is started. The unit used for the data transfer is registered in the active unit table 92. As a result of the search, the unit is registered in the active unit table 92, that is, used by another block data transfer. If not, the block data transfer is not activated.
In this case, the above procedure is repeated as long as there is a request for block data transfer.

The extended scheduler 90 first stores the head address of the data area to be transferred designated as the block data transfer request and the transferred data in the address counter 11 of the sending unit of the data transfer source and the receiving unit of the data transfer destination. Two address slots are issued to set the head addresses of the storage areas, respectively, and block data transfer is started. The address slot is a slot for setting an address in the address counter 11 of the unit. The unit for which an address is to be set is a receiving unit, and the address to be set is data. The data transmission unit is a scheduler. Each unit constantly monitors the status line 3, and upon detecting an address slot, if itself is designated as a receiving unit, activates the data fetching means 14 and sends the data on the data line 4 after the occupancy confirmation time has elapsed. The received address is set in the address counter 11. Further, after the state transition time, an acceptance state is output to the state line 5. The extended scheduler 90 monitors the occupation line 3, and upon detecting an address slot, activates the state confirmation means 16 and checks the state information sent on the state line 5 after a state transition time from the occupation confirmation time. It is confirmed that the transmitted address is received by the specified receiving unit and set in the address counter 11. Upon confirming the setting of the addresses in the two address counters 11, the transfer source unit and the transfer destination unit specified in the block data transfer request are registered in the in-use unit table 92, and the data is stored in the secured remaining issue number counter 95. The number of data transfers determined from the data size specified in the transfer request is set, and the first data slot is issued.

In the occupation information of the data slot, a transfer source unit is specified as a transmission unit, and a data transfer destination unit is specified as a reception unit. Each unit always monitors the occupied line 3. When detecting a data slot, if the unit itself is designated as the sending unit, the unit activates the data output means 13 and activates the address designated by the address counter 11. The data is output to the data line 4 after the occupation confirmation time, and the address counter is incremented. When the receiving unit is designated as itself, the data fetching means 14 is activated to fetch the data transmitted on the data line 4 after the occupation confirmation time, and the data writing means 18 is activated to change the address of the address counter 11. The specified data is written to the data memory 8 and the address counter 11 is incremented. Further, it activates the state output means 15 and outputs an acceptance state to the state line 5 after the state transition time.

The extended scheduler 90 monitors the occupation line 3, and upon detecting a data slot, activates the state confirmation means 16 and transmits the state information transmitted on the state line 5 after the state transition time from the occupation confirmation time. To confirm that the data transfer by the data slot has been performed normally.

The extended scheduler 90 is configured to continuously perform the number of data transfers determined by the size of the data specified as the block data transfer request in order to transfer the block data.

Upon confirming the setting of the addresses in the two address counters 11, the extended scheduler 90 issues the first data slot. Simultaneously with the issuance of the data slot, the remaining issue counter 95 is decremented, and the issuance interval timer 96 is set to an issuance interval time value determined by the time required for the memory to process the access. The issue interval timer 96 is configured to be decremented by a clock.
When the value of 6 becomes 0, data slot issuance is repeated until the remaining issue number counter 95 becomes 0.

If the setting of the address by the address slot or the transfer of the data by the data slot fails, the data transfer being executed at that time is stopped, and the resources secured for the execution are released. Restart the transfer.

When the data transfer by the last data slot is performed normally, that is, when the requested block data transfer is completed, the extended scheduler 90 deletes the block data transfer request from the block data transfer request buffer 91, At the same time, the registration of the sending unit and the receiving unit used for the block data transfer is deleted from the in-use unit table 92. Further, the set of the remaining issue number counter 95 and the issue interval timer 96 that have been used is released, and the transfer of the block data ends.

[0030]

According to the present invention, the efficiency of occupancy control in the pipeline bus for the purpose of improving the data transfer throughput can be improved, and the data transfer throughput can be further increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a pipeline bus of the present invention.

FIG. 2 is a block diagram showing a configuration of a sending unit in the pipeline bus of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a receiving unit in the pipeline bus of FIG. 1;

FIG. 4 is a block diagram showing a configuration of a scheduler in the pipeline bus of FIG. 1;

FIG. 5 is a diagram showing a configuration of a pipeline bus according to one embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a module 20 in the embodiment of FIG.

FIG. 7 is a diagram showing a configuration of an expansion module 90 in the embodiment of FIG. 5;

FIG. 8 is a diagram showing a time relationship among signals constituting slots in the pipeline bus of FIG. 1;

[Explanation of symbols]

 1 requester 2 server 3 occupancy line 4 data line 5 status line 6 slot definer line 9 scheduler

Claims (1)

(57) [Claims] In a bus in which a data transfer cycle is shortened by physically dividing a bus and a data transfer throughput is improved, a unit constituting a system includes:
An occupancy line indicating the occupation state of the physically divided partial bus, a data line, and a state line indicating the result of data transfer are connected to each other, and occupation information on the occupation line, data on the data line, and data on the state line A scheduler that transfers data transfer results in one direction and arbitrates a bus use request from a unit that attempts to perform data transfer,
A pipeline bus wherein an identifier of a unit using a partial bus is given as occupation information, and each unit independently outputs data and receives data based on designation of occupation information given by a scheduler.