JPH01187662A - Channel device - Google Patents

Abstract

PURPOSE:To relax the limitation of channel command chain time by using effectively time from when an input/output device terminates the transfer of a necessary number of data to when the termination state of the input/output device is transmitted to a channel device. CONSTITUTION:By knowing that the transfer of the necessary number of data is terminated by an input/output device 5, a channel control part 3 starts the preprocessing of a command chain processing by a termination state report following the termination processing of the data transfer. Consequently, the processing in a channel device 4 can be started in parallel with the processing to prepare the termination state by the input/output device 5. Thus, the limitation of the command chain time in the channel device 4 is relaxed and the generation of command overrun can be decreased without increasing the quantity of hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer device, and particularly to a channel device capable of performing high-speed command chain processing.

[Conventional technology]

In a conventional data transfer device, as shown in FIG. It controls the device 5 and transfers data between the memory 2 and the input/output device 5 via the channel control unit 3, and performs data transfer termination processing and command chain processing based on the completion status report from the input/output device 5. .

After the completion status report from the input/output device 5, the channel control unit 3 stores the glued data from the input/output device 5 remaining in the data buffer in the channel device 4 into the memory 2 and the channel device for which the completion status report was received. After setting the control information necessary for the termination process, etc., the termination process and command chain process are performed. If the command chain processing is not completed within a certain period of time, a command overrun failure will occur in the input/output device 5, so the channel control unit 5 will issue commands such as those shown in JP-A-61-5260 and JP-A-60-136848. Measures are being taken to shorten chain processing time.

The above-mentioned conventional technology proposes a means for speeding up the processing after the completion status report is generated from the input/output device, and the allocation of command chain time between the channel device and the input/output device is It wasn't taken into account.

An object of the present invention is to realize a channel device that can effectively utilize the time from the end of transfer of the number of data required by the input/output device to the time when the end state of the input/output device is notified to the channel device. The purpose of the above is to reduce the number of command chain times required by I/O devices and reduce the amount of hardware required for channel devices (and reduce the occurrence of command overruns). The channel device informs the channel control unit of the completion of data transfer by reporting the end status of the input/output device in advance, and the channel control unit terminates the data transfer. process,
This is accomplished by allowing preprocessing of the command chain with subsequent completion status reports.

[Effect]

Upon learning that the required number of data transfers for the input/output device have been completed, the channel control unit starts data transfer finalization processing and subsequent preprocessing for command chain processing by reporting the completion status. This allows the input/output device to start processing in the channel device in parallel with the processing for creating the end state, thereby easing the restriction on the command chain time in the channel device.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

The channel device 4 includes a buffer circuit 41, a buffer control circuit 42, a transfer end report 405, and an end status report 404.
It consists of an OR circuit 45. In addition to performing normal buffer control, the buffer control circuit 42 also performs an operation of sending the read data remaining in the buffer circuit 41 to the channel control section 3 via the bus 300 in the case of a read command based on the output of the OR circuit 45. . Further, the channel device 4 transmits the transfer end report 405 and the end state report 404 to the channel control unit 3 as interrupt signals.

The input/output bag @5 is the i/Q control circuit 51. selector 52 register 55. Subtractor 54. Zero detection circuit 55. and an AND circuit 56. In addition to normal input/output device control, the i/Q control circuit 51 also controls an initial value signal 501 indicating the number of transfer bytes determined by the record format of the device and a selector 52.
selection signal 502. Set signal 504 of register 53.
Zero detection signal 50 indicating that the value of register 53 is zero
The 5° selector 52 also controls the permission signal 506 to output 5 as the transfer end report 405.
Either input of the initial value signal 501 from i51 and the output signal 512 from the subtracter 54 is transmitted to the selector output signal 510 by the selection signal 502. Register 56 stores selector output signal 510 in response to set signal 504 . The subtracter 54 extracts 1'5! from the register output signal 511.
: Output the subtracted value. Zero detection circuit 55 outputs zero detection signal 505 when the value of register output signal 511 is zero.

Next, the operation of the embodiment will be explained using a read type command as an example. The input/output device 5 receives a read command instruction from the channel device 4 and sends an initial value signal 501 to the number of bytes of data determined by the record format of the input/output device.
This is transmitted to the selector 52 by. The selection signal 502 outputs the value of the initial value signal 501 to the selector output 510, stores the number of data bytes in the set signal 504 register 53, and sets the output permission signal 503 of the zero detection signal 505 of the zero output circuit 55 to logic 1. shall be. The control circuit 51 reads data from the input/output device, outputs the data to the data bus 4 (IN), and requests the channel device 4 to transfer the data in response to a data request m402.The channel device 4 transfers the data on the data bus 401 to the buffer circuit 41. The receipt of the data is transmitted to the input/output unit [5] by the stored data response @ 403. In this way, each time one byte is transferred, the output 512 of the subtraction circuit 54 is
is output from the selector 5 by the selection signal 502 of the selector 52.
101C transmission set signal 504 register 53K
Store and reduce the number of bytes by 1.

When the contents of the register 55 become zero, the zero detection circuit 55 outputs a zero detection signal 505 and transmits a transfer completion report 405 to the channel device 4 via the AND circuit 56.

Thereafter, in response to the zero detection signal 505, the Lo control circuit 51 checks whether the data has been read correctly using a check code or the like, creates an end state, and transmits an end state report '404 to the channel device 4.

The channel device 4 transmits the read data remaining in the buffer circuit 41 to the bus 50 by transmitting the transfer completion report 405 to the buffer control circuit 42 via the OR circuit 43.
0 to the channel control unit 3. The channel control unit 5 detects the transfer end report 405 via the channel device 4, performs data transfer end processing of the channel device 4, performs all preprocessing in preparation for processing the subsequent end state report 404, and ends.

Wait for status report 404. When the end status report 404 is detected, the channel control unit 3 uses the channel cofund language (CCW).
It also checks the termination status (DSB) of the input/output device 5, and immediately starts command chain processing if necessary.

Therefore, in this embodiment, the termination process of the input/output device and the termination process of the channel and channel control unit can be executed in parallel, so the restriction on the command chain time in the channel control unit is relaxed, and the occurrence of command overruns is reduced. There is an effect that can be done.

〔Effect of the invention〕

According to the present invention, the channel controller can use the time during which the input/output device is creating a termination state to complete data transfer and pre-process the next command chain, thereby easing command chain time restrictions and This has the effect of reducing the occurrence of command overruns without increasing the amount.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional data transfer system. In the figure, 1, 1: central processing unit, 2: memory, 3: channel control unit, 4: channel device, 5: input/output device, 4
1; Buffer circuit, 42: Buffer control circuit, 45; OR circuit, 51: c10 control circuit, 52°; Selector, 56; Register, 54; Subtractor, 55; Zero detection circuit,
404: Completion status report, 405: Transfer completion report. Representative Patent Attorney Katsuo Ogawa

Claims (1)

[Claims] 1. In a channel device installed between an input/output device and a channel control unit, which controls the input/output interface and transfers data between the input/output device and the memory device via the channel control unit, means for notifying the channel device of the end state of the input/output operation, and means for notifying the channel device of the end of transfer of a required number of data within the input/output device, A channel device characterized by transmitting information to a channel control section.