JPH042981B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer control device, and is particularly suitable for application when working as a part of an input/output control device that collectively controls a plurality of input/output devices having different data transfer speeds. It concerns a data transfer control device.

Input/output operations in modern electronic computer systems are controlled by channel devices executing channel command words in main memory separately from the central processing unit. Therefore, the central processing unit is freed from the burden of controlling input/output operations and can efficiently execute programs.

On the other hand, channel devices are forced to carry a heavy burden because they control input/output operations in addition to data transfer for input/output devices.

Particularly in large information processing systems in which the number of input/output devices is large and the configurations and functions of the channels, commands, and words are complex, the burden on the channel devices becomes even greater.

Conventionally, in order to reduce the burden on such channel devices, a part of the control of the input/output devices has been taken over by an input/output control device.

Also, when a channel device is connected to a large number of input/output devices, especially a group of input/output devices with high data transfer rates such as magnetic disk devices, the response speed of the channel device may be insufficient for these input/output devices. In cases where the response from the time a data transfer request is received until the time the data transfer is performed is not in time, a data buffer circuit is often used to temporarily store the data transfer contents in order to compensate for this.

That is, in the magnetic disk device described above, a clock signal is obtained by the rotation of the magnetic recording medium, and data is written in synchronization with this clock signal. At this time, data to be written is requested from the channel device, Data can be written to a specified position on the medium only when data is obtained within a certain period of time after this request. Therefore, if the channel device is unable to respond within a certain period of time each time the data request is made, the data is stored in the data buffer circuit prior to the data request, thereby replacing the channel device. Data requested by the magnetic disk device is sent from the data buffer circuit. As a result, if the data buffer circuit responds quickly to data requests from the magnetic disk device, the channel device operates asynchronously with the magnetic disk device, and due to fluctuations in the amount of multiprocessing, Even if the response to the above data request is temporarily delayed, it is not a problem.

Further, data transfer between the data buffer circuit and the channel device is asynchronous with data transfer between the data buffer circuit and an input/output device such as a magnetic disk device, and can be performed independently.

Incidentally, conventionally, control of data transfer between the data buffer circuit and the channel device has generally been performed using an interlock system.

FIG. 1 is a diagram for explaining this interlock system, and FIG. 2 is a diagram showing interface signal lines through which data signals and control signals used in the interlock system shown in FIG. 1 are transmitted.

In FIG. 2, 10 is a channel device, 20 is an input/output control device including a data buffer circuit, BUS is a bidirectional data bus, TGI ₁ , TGI ₂ , TGO ₁ ,
TGO ₂ is a tag-in/tag-out line that constitutes the control bus, and these tag-in/tag-out lines have different functions depending on the direction of the data bus. That is, when sending data from the channel device 10 to the input/output control device 20, the tag-in lines TGI ₁ and TGI ₂ alternately transmit request signals R ₁ and R ₂ representing data requests, and the tag-out line TGO ₁ , TGO ₂ transmits sending signals S 1 and S 2 indicating that data exists on the data bus BUS (being sent from the channel device), and also transmits sending signals S ₁ and S ₂ when data is sent from the input/output control device 20 to the channel device 10. are the tag-in lines TGI ₁ and TGI ₂
are alternately connected to the input/output control device 2 on the data bus BUS.
In addition to transmitting a sending signal indicating that there is data being sent from 0, the tagout line
For TGO ₁ and TGO ₂ , the channel device 10 is a data bus.
Sends a receive signal indicating that data on the BUS is being received.

Now, as an example, referring to FIG. 1, the above-mentioned interlock system will be specifically explained in the case where data is transferred from the channel device 10 to the input/output control device 20.

First, as shown in FIG. 1, the request signal R ₁
is connected to the input/output control device 20 via the tag-in line TGI ₁ .
to the channel device 10. Then, this signal R ₁ goes through a delay on the signal table and a response operation time in the channel device as shown by arrow i, and then the first data D ₁ is transferred from the channel device onto the data bus as shown in FIG. 5. send it out. Then, after a predetermined period when the data _D1 on the data bus is finalized, the sending signal _S1 rises as shown in FIG.

This sending signal S ₁ is connected to the tagout line TGO ₁
is transmitted to the input/output control device 20 via the input/output controller 20, thereby stopping the sending of the request signal _R1 as shown by arrow j. Then, the fact that the sending of the request signal _R1 has been stopped is transmitted to the channel device 10 as shown by arrow l, and the sending of the sending signal _S1 shown in FIG. 2 is stopped.

Furthermore, to stop the sending of the request signal _R1 , the sending of the request signal _R2 corresponding to the second data request _shown in FIG.
Invoke as shown. This request signal R ₂
As shown in _FIG . 4, the response _to
The response operations are performed in exactly the same manner as the response operations shown by the arrows i to k between FIG. 1 and 2.

This operation causes the input/output device to send a data request and then continue with a data request that confirms the data sending in response.
Further, the channel device starts data transmission after receiving a data request, confirms that this request has been completed, finishes data transmission, and responds to the next data request. Therefore, the time spent on responses as shown by arrows i and j in FIG.
time, and the reciprocal of this is the data transfer rate.
The time required for the response indicated by the arrows i and j includes the time required for the signal to be transmitted on the interface cable, so the data transfer rate depends on the length of the interface cable. As a result, input/output controllers that control input/output devices with high data transfer rates are restricted from increasing the length of their interface cables beyond a certain level, or are otherwise required to use very large capacity data buffer circuits. In addition, there was an inconvenience in that it was necessary to forcibly limit the access frequency of the input/output device.

In order to avoid this, it is necessary to request data only for a certain period of time without waiting for the response confirmation shown by arrow j in FIG.
The system in which no response confirmation is performed is called an offset interlock, and has conventionally been applied to control data transfer to input/output devices having low data transfer speeds, for example.

However, if this offset interlock method is used as is for data transfer between an input/output control device and a channel device, the data transfer rate will be the same as that of the input/output device that has the maximum data transfer rate connected to the input/output control device. It is necessary to transfer data between the channel device and the data buffer circuit.

Therefore, when data is transferred to an input/output device having a low data transfer speed, a situation occurs in which the input speed to the data buffer circuit is high and the output speed is low, and the data buffer circuit is There was an inconvenience that made it difficult to use it efficiently.

Thus, the present invention aims to eliminate such inconvenience, and the purpose is to mediate data transfer between a plurality of input/output devices and channel devices with different data transfer speeds, and temporarily transfer the data transfer contents. A data transfer control device comprising a data buffer circuit for storing data and controlling data transfer between the channel device and the input/output device, the device including input/output device identification means for identifying an input/output device to which data should be transferred; A speed at which the data transfer speed between the channel device and the data buffer circuit is changed to match the data transfer speed between the input/output device to which data is to be transferred and the data buffer circuit based on the output of the input/output device identification means. This is achieved by providing a control means, and one embodiment thereof will be described in detail below with reference to the drawings.

FIG. 3 is a diagram illustrating a signal system of a channel device in which the present invention is implemented, a plurality of input/output devices, and an input/output control device provided between these channel devices and the input/output devices, and FIG. Tagout line shown in figure
A diagram illustrating TGO ₁ , TGO ₂ and tag-in lines TGI ₁ , TGI ₂ and signal waveforms on the data bus,
FIG. 5 is a diagram illustrating the detailed configuration of the data buffer circuit and speed control section shown in FIG. 3.

In FIG. 3, 10 is a channel device, 20 is an input/output control device, 30 ₁ to 30 ₃ are a plurality of input/output devices, and BUS is a data bus provided between the channel device 10 and the input/output control device 20. TGO ₁ , TGO ₂ , TGI ₁ , TGI ₂ have the same functions as the tag-out lines TGO ₁ , TGO ₂ and tag-in lines TGI ₁ , TGI ₂ shown in Fig. 2, respectively, and BUS' is the input line. Output control device 20 and a plurality of input/output devices 30 ₁ -
30 ₃ common data bus, ITI
is the interface tag-in line, and ITO is the interface tag-out line. Interface tag-in line is common data bus
When data is transferred from the input/output devices 30 ₁ to 30 ₃ to the input/output control device 20 on the common data bus BUS', a sending signal indicating that data exists on the common data bus BUS is transmitted, and the data is transferred on the common data bus BUS. When data is transferred from the output control device 20 to the input/output devices 30 ₁ to 30 ₃ , a request signal representing a data request is transmitted. Similarly, the interface tag out line ITO is the input/output device 30.
When data is transferred from ₁ to 30 ₃ to the input/output control device 20, a receive signal indicating that data on the common data bus BUS' is being received is transmitted, and conversely, from the input/output control device 20 to the input/output device common data bus when data is transferred to
It transmits a sending signal indicating that data exists on BUS'.

In addition, the input/output control device 20 includes a data buffer circuit 21 as a component for controlling data transfer, and controls data transmission and reception between the data buffer circuit 21 and the data bus BUS, and also controls the tag-in line/tag-out line TGI. ₁ , TGI ₂ , TGO ₁ ,
A data transfer main control circuit that sends and receives signals on the TGO ₂ , a speed control timer 25 that provides timing signals set at predetermined intervals to the data transfer main control circuit 22, and setting of the timing signal V in the speed control timer 25. A register 24 in which IO identification information ID is stored and a common data bus to indicate the interval according to the type of input/output device during data transfer.
It has an input/output interface circuit that controls data transmission and reception between BUS' and the data buffer circuit 21, and also transmits and receives signals on the interface tag-in line ITI and interface tag-out line ITO.

Now, when performing input/output operations to the input/output devices 30 ₁ to 30 ₃ , selection of the input/output device is instructed by a command from the channel device 10 prior to data transfer. Therefore, information indicating the type of input/output device selected thereby is held in the input/output control device 20, and in the present invention, the information indicating the type of the input/output device selected is
It is stored in the identification information register 24. During data transfer, the content ID of this IO identification information register 24 controls the speed control timer 25, so
The speed control timer 25 repeatedly generates a timing signal V having a time interval (given by the reciprocal of the speed) corresponding to the data transfer speed required by the input/output device currently transferring data. As a result, the timing signal V causes the data transfer main control circuit 22 to transfer data on the data bus BUS at a data transfer rate that substantially matches the data transfer rate on the common data bus BUS'.
It goes without saying that the data transfers on both data buses are asynchronous with each other, and the timing difference between them is subject to change.

That is, the data buffer circuit absorbs slow fluctuations in the response of the channel device.

In this way, in the present invention, since the data transfer speeds on the two data buses via the data buffer circuit 21 are equal, the data buffer circuit 2
1. It is only necessary to have a storage capacity sufficient to store the maximum number of data that can be sent (or requested) by the input/output device within the maximum response time of the channel device 10. In other words, there is no longer a need for an extra storage capacity that is proportional to the product of the data transfer rate difference and the data transfer duration time as in the prior art.

Further, the present invention employs an offset interlock system, which will be explained below with reference to FIGS. 4 and 5.

Figure 4 shows each interface signal and data signal when data is transferred from the input _/ output control device _to the channel device. Figure 2 shows the receive signal _R1 on the tagout line _TGO1 ,
Figure 3 shows the sending signal on tag-in line TGI ₂ .
₄ shows the receive signal R ₂ on the tag-out line TGO ₂ , and FIG. 5 shows the data signal. The sending signals S ₁ and S ₂ are both given a minimum repetition period by T, and this period T is twice the minimum period of the output of the speed control timer 25, as will be described later.

Now, when the first data D ₀ is sent out on the data bus as shown in Figure 5, immediately after that, the sending signal S ₁ as shown in Figure 1 is sent to the tag-in line.
Occurs on TGI ₁ . Then, the generation of this sending signal _S1 is transmitted to the channel device, and the arrow i
As shown in , a receive signal R ₁ is sent onto the tag-out bus TGO ₁ in response to this sending signal S ₁ . At this time, since data D ₀ on the data bus has already been stored in a data buffer (not shown) on the channel device side, the channel device retrieves the data from this data buffer.

In addition, as shown in FIG. 1, the sending signal S ₁
does not wait for the generation of the receive signal _R1 , and the period T
After continuously transmitting for approximately half of the time, the transmitting is terminated. The end of sending this sending signal _S1 is indicated by arrow k.
As shown by arrow 1, it triggers the transmission of the sending signal _S2 on the other tag-in line TGI ₂ , which indicates the transmission of the next data _D1 , and also triggers the transmission of the receive signal _R1, as shown by arrow l. It becomes a challenge. Furthermore, the completion of transmission of this receive signal R ₁ permits transmission of the next receive signal R ₂ on the other tag-out line. That is, on the condition that the second sending S ₂ is given to the channel device as shown by arrow i' and the end of sending of the first receive signal R ₁ occurs as shown by arrow m. The th receive signal _R2 is sent out. Thereafter, this response is alternately repeated between the tag-in and tag-out lines TGI ₁ , TGI ₂ , TGO ₁ , and TGO ₂ forming a pair.

Next, the tag-in line TGI ₁ shown in FIGS. 1 and 3,
A specific circuit for generating signals on TGI ₂ will be explained with reference to FIG.

In FIG. 5, 21 is a data buffer circuit, 22 is a data transfer main control circuit, 24 is an IO identification information register, 25 is a speed control timer, common data bus BUS', data bus BUS, interface tag In-line ITI, tag-in line TGI ₁ ,
TGI ₂ is the same as in Figure 3.

The data buffer circuit 21 is a buffer memory.
A switching circuit MLT that distributes data from the BUF and common data bus BUS' to each address in the buffer memory BUF, a selection circuit SEL that selects the contents of each address in the buffer memory BUF, and a buffer memory
An in counter CNTi increments with a signal from the interface tag in ITI line each time data is stored in the BUF, an out counter CNTo increments each time data is sent out from the buffer memory BUF, and the counted values of both counters CNTi and CNTo. It is composed of a comparator CMP that compares the magnitude of .

The data transfer main control circuit 22 also includes a flip-flop FF and an AND gate AND ₁ ,
has AND ₂ .

Although FIG. 5 only shows the configuration used to transfer data from the input/output control device 20 to the channel device 10, a similar configuration is actually used for data transfer in the opposite direction. Separately provided.

To explain how it works, the common data bus
Data sent from the input/output device from the BUS' is stored one after another in the buffer memory BUF via the switching circuit MLT, and at this time, the in-counter CNTi increments the count by 1 each time data is stored.

Since the contents of the in-counter CNTi increased in this way are larger than the contents of the out-counter CNTo, "1" is output from the comparator CMP.
Therefore, the AND gates AND ₁ and AND ₂ pass the output of the flip-flop FF. The outputs of flip-flop FFs are complementary to each other, that is, one is “1”
When , the other is "0", so the output of the AND gates AND ₁ and AND ₂ is also one (for example
TGI ₁ side) becomes “1” and the other side (for example, TGI ₂ side) becomes “0”.

On the other hand, the output "1" of the comparator CMP is also given to the speed control timer 25, which enables the speed control timer 25 to count the clock O/
When the target count value specified by the contents of the identification information register 24 is reached, a pulse-like timing signal V is generated and the counter itself is reset. This timing signal V is applied to the flip-flop
Inverts FF and increments out counter CNT ₀ . The next data from the buffer memory BUF is then read out and sent onto the data bus BUS. As a result, if the contents of the in-counter CNTi and the out-counter CNT ₀ become equal, the outputs of the AND gates AND ₁ and AND ₂ will both be “0”, but the next data will be transferred to the common data bus.
Since the contents of the in-counter CNTi are still greater than the contents of the out-counter CNT ₀ when stored from the BUS′ to the buffer memory BUF,
The AND gates AND ₁ and AND ₂ output the output of the flip-flop FF, that is, the inverted contents of the previous logical values.

In this embodiment, the speed control timer 25
Since the target count value instructed by is a value obtained by dividing half of the period T shown in FIG. 4 by the period of the clock O/, data is sent onto the data bus BUS every T/2 period. And this period T/2 is
Since the contents of the IO identification information register 24 are set in accordance with the data transfer speed of the input/output device, it is possible to substantially match the input speed and output speed of data to the buffer memory BUF.

As explained above, according to the present invention, it is possible to set the data transfer rate between a channel device and a data buffer circuit in accordance with the data transfer rate between a plurality of input/output devices having different data transfer rates and the data buffer circuit. Therefore, it is only necessary to prepare a data buffer circuit with a storage capacity sufficient to store the maximum number of data that can be sent or requested by the input/output device within the maximum response time of the channel device, and it is possible to save data at low cost. It becomes possible to provide a transfer control device.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a conventional interlock system, FIG. 2 is a diagram showing interface signals used for data transfer between a channel device and an input/output control device, and FIG. 3 is a diagram for explaining an embodiment of the invention. FIG. 4 is an explanatory diagram of the offset interlock system implemented by the present invention, and FIG. 5 is a diagram illustrating the main parts used for data transfer control of the present invention. be. R ₁ , R ₂ ...Request or receive signal, S ₁ ,
S ₂ ... Sending signal, D ₁ , D ₂ , D ₃ , D ₄ ...
Data signal, TGI ₁ , TGI ₂ ...Tag-in line,
TGO ₁ , TGO ₂ ... tag-out line, BUS ... data bus, 10 ... channel device, 20 ... input/output control device, 30 ₁ to 30 ₂ ... input/output device, 21
...Data buffer circuit, 22...Data transfer main control circuit, 23...I/O interface circuit, 24...IO identification information register, 25...Speed control timer.

Claims (1)

[Scope of Claims] 1. A data buffer circuit that mediates data transfer between a plurality of input/output devices having different data transfer speeds and a channel device, and temporarily stores the contents of the data transfer; A data transfer control device for controlling data transfer between input/output devices, the device comprising: input/output device identification means for identifying an input/output device to which data should be transferred; and an output from the input/output device identification means to identify the channel device. A data transfer characterized by comprising: speed control means for switching the transfer speed so that the data transfer speed between the data buffer circuits matches the data transfer speed between the input/output device to which data is to be transferred and the data buffer circuit; Control device.