JPS5569834A - Data transfer controller - Google Patents

Data transfer controller

Info

Publication number
JPS5569834A
JPS5569834A JP14235678A JP14235678A JPS5569834A JP S5569834 A JPS5569834 A JP S5569834A JP 14235678 A JP14235678 A JP 14235678A JP 14235678 A JP14235678 A JP 14235678A JP S5569834 A JPS5569834 A JP S5569834A
Authority
JP
Japan
Prior art keywords
data
inputted
input
output unit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14235678A
Other languages
Japanese (ja)
Inventor
Norikazu Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14235678A priority Critical patent/JPS5569834A/en
Publication of JPS5569834A publication Critical patent/JPS5569834A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase a data processing speed by make it possible to transfer data without waiting for the data processing operation of an input-output unit when a data transfer mode is set.
CONSTITUTION: A data transfer mode start instruction from a computer is inputted to decoder 14 of controller 2, and consequently start instruction signal 41 is outputted to set FF50. On the other hand, strobe signal 31 from the computer is inputted to set FF51 and in-process display signal 39 is outputted to an input-output unit. Next, the mentioned-above unit generates response signal 36 to reset FFs 50 and 51. Then, a write instruction is inputted to decoder 14 to set FFs 50 and 51 again. On the basis of data request signal 40, data is inputted through data bus 33, sent to buffer register 18, and then transferred to buffer register 25 of controller 4 before being inputted to the input-output unit. Once the input-output unit completes data processing, process end signal 36 is generated to reset FFs 51 and 50. In this way, an interface ready mode is set between the computer and input-output unit.
COPYRIGHT: (C)1980,JPO&Japio
JP14235678A 1978-11-20 1978-11-20 Data transfer controller Pending JPS5569834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14235678A JPS5569834A (en) 1978-11-20 1978-11-20 Data transfer controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14235678A JPS5569834A (en) 1978-11-20 1978-11-20 Data transfer controller

Publications (1)

Publication Number Publication Date
JPS5569834A true JPS5569834A (en) 1980-05-26

Family

ID=15313463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14235678A Pending JPS5569834A (en) 1978-11-20 1978-11-20 Data transfer controller

Country Status (1)

Country Link
JP (1) JPS5569834A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006334181A (en) * 2005-06-03 2006-12-14 Sanyo Electric Co Ltd Waterproof shaver with built-in sound generation means

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006334181A (en) * 2005-06-03 2006-12-14 Sanyo Electric Co Ltd Waterproof shaver with built-in sound generation means

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