JPS5697154A - Interruption control system for information processor - Google Patents

Interruption control system for information processor

Info

Publication number
JPS5697154A
JPS5697154A JP17349679A JP17349679A JPS5697154A JP S5697154 A JPS5697154 A JP S5697154A JP 17349679 A JP17349679 A JP 17349679A JP 17349679 A JP17349679 A JP 17349679A JP S5697154 A JPS5697154 A JP S5697154A
Authority
JP
Japan
Prior art keywords
execution
cpu11
register
unit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17349679A
Other languages
Japanese (ja)
Other versions
JPS6252900B2 (en
Inventor
Toshihiro Akiyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP17349679A priority Critical patent/JPS5697154A/en
Publication of JPS5697154A publication Critical patent/JPS5697154A/en
Publication of JPS6252900B2 publication Critical patent/JPS6252900B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To speed up the interrupting processing speed, by shunting the operation process up to now, when an interrupting request is present for the additional processor during the execution.
CONSTITUTION: If an interruption is requested to CPU11 externally during the execution of instruction of the additional processor 12, the unit 12 transfers the content of the operation register 28 executed up to now by the control memory 27 to the shunt register 25. Further, the content of the register 28 is shunted to the memory unit via the common bus 15. When the shunting is finished, the control of the control memory 27 transfers the shunt end signal to the CPU11, and CPU11 performs interruption processing requested. When the interruption processing by CPU11 is finished, the retrial command is transferred to the unit 12 via the bus 15. The control memory 27 of the unit 12 returns the shunted information in advance to the register 28 from the memory unit and restarts the execution on the way of execution of instruction interrupted before.
COPYRIGHT: (C)1981,JPO&Japio
JP17349679A 1979-12-29 1979-12-29 Interruption control system for information processor Granted JPS5697154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17349679A JPS5697154A (en) 1979-12-29 1979-12-29 Interruption control system for information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17349679A JPS5697154A (en) 1979-12-29 1979-12-29 Interruption control system for information processor

Publications (2)

Publication Number Publication Date
JPS5697154A true JPS5697154A (en) 1981-08-05
JPS6252900B2 JPS6252900B2 (en) 1987-11-07

Family

ID=15961584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17349679A Granted JPS5697154A (en) 1979-12-29 1979-12-29 Interruption control system for information processor

Country Status (1)

Country Link
JP (1) JPS5697154A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5960551A (en) * 1982-09-30 1984-04-06 Fujitsu Ltd Memory access controlling system
JPH02148164A (en) * 1988-11-30 1990-06-07 Hitachi Ltd Processor and its drawback and return method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5960551A (en) * 1982-09-30 1984-04-06 Fujitsu Ltd Memory access controlling system
JPH0152775B2 (en) * 1982-09-30 1989-11-10 Fujitsu Ltd
JPH02148164A (en) * 1988-11-30 1990-06-07 Hitachi Ltd Processor and its drawback and return method

Also Published As

Publication number Publication date
JPS6252900B2 (en) 1987-11-07

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