JPS57176442A - Information processing system - Google Patents

Information processing system

Info

Publication number
JPS57176442A
JPS57176442A JP6215881A JP6215881A JPS57176442A JP S57176442 A JPS57176442 A JP S57176442A JP 6215881 A JP6215881 A JP 6215881A JP 6215881 A JP6215881 A JP 6215881A JP S57176442 A JPS57176442 A JP S57176442A
Authority
JP
Japan
Prior art keywords
external device
memory
data
transfer
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6215881A
Other languages
Japanese (ja)
Inventor
Hajime Saito
Yutaka Takano
Yasuyuki Yamakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6215881A priority Critical patent/JPS57176442A/en
Publication of JPS57176442A publication Critical patent/JPS57176442A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

PURPOSE:To enable the transfer in high speed determined with the cycle time of a memory for data transfer with an external device, by providing a switcher in a transmission line between the memory and the external device and enabling to switch and connect a memory and a data bus. CONSTITUTION:When a data transfer request is given from an external device D to a processor P via a signal line L1, the data to be transferred is moved to a data transfer area M'. When a request from the external device D is present and data is set to the M', a switcher K1 is switched to the external device D through the start from the processor P for data transfer. The transfer speed in this case can be made equal to the cycle time of a memory M and not affected with the data bus line. During transfer, the processor P can execute another program at the same time. In making data transfer from the external device D to the memory M, the similar processing is made with a switcher K2.
JP6215881A 1981-04-24 1981-04-24 Information processing system Pending JPS57176442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6215881A JPS57176442A (en) 1981-04-24 1981-04-24 Information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6215881A JPS57176442A (en) 1981-04-24 1981-04-24 Information processing system

Publications (1)

Publication Number Publication Date
JPS57176442A true JPS57176442A (en) 1982-10-29

Family

ID=13192019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6215881A Pending JPS57176442A (en) 1981-04-24 1981-04-24 Information processing system

Country Status (1)

Country Link
JP (1) JPS57176442A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59133629A (en) * 1983-01-20 1984-08-01 Hitachi Ltd Dma transfer control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59133629A (en) * 1983-01-20 1984-08-01 Hitachi Ltd Dma transfer control system

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