JPS54137940A - Multi-data processor - Google Patents

Multi-data processor

Info

Publication number
JPS54137940A
JPS54137940A JP4537378A JP4537378A JPS54137940A JP S54137940 A JPS54137940 A JP S54137940A JP 4537378 A JP4537378 A JP 4537378A JP 4537378 A JP4537378 A JP 4537378A JP S54137940 A JPS54137940 A JP S54137940A
Authority
JP
Japan
Prior art keywords
address signal
data transfer
circuit
signal line
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4537378A
Other languages
Japanese (ja)
Other versions
JPS592942B2 (en
Inventor
Yoshiaki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4537378A priority Critical patent/JPS592942B2/en
Publication of JPS54137940A publication Critical patent/JPS54137940A/en
Publication of JPS592942B2 publication Critical patent/JPS592942B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To make the switching control of a double system possible by separating an address signal line in a common bus into a data transfer address signal line and a system address signal line in a multi-data processor.
CONSTITUTION: Common bus 20 is provided with data transfer address signal line 21 and system address signal line 22. At the time of data transfer, data transfer control circuit 15 of data processor 19 sends out data transfer address signal (n), opposite unit 19 discriminates that signal (n) inputted to discrimination crcuit 23 is its own data transfer address, and circuit 15 transfers data. At the time of switching to the double system, doubling switching control circuit 27 of switching control circuit 18 outputs transfer address signal (n) and system address signal (o). Discrimination circuit 24 of circuit 19 recognizes signal (o) to be the address signal of its own system and doubling switching circuit 16 attains the switching between the in-use system and stand-by system.
COPYRIGHT: (C)1979,JPO&Japio
JP4537378A 1978-04-19 1978-04-19 Multi data processing device Expired JPS592942B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4537378A JPS592942B2 (en) 1978-04-19 1978-04-19 Multi data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4537378A JPS592942B2 (en) 1978-04-19 1978-04-19 Multi data processing device

Publications (2)

Publication Number Publication Date
JPS54137940A true JPS54137940A (en) 1979-10-26
JPS592942B2 JPS592942B2 (en) 1984-01-21

Family

ID=12717455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4537378A Expired JPS592942B2 (en) 1978-04-19 1978-04-19 Multi data processing device

Country Status (1)

Country Link
JP (1) JPS592942B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5717072A (en) * 1980-05-19 1982-01-28 Data General Corp Uncompetitive computer circuit netword having no master

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5717072A (en) * 1980-05-19 1982-01-28 Data General Corp Uncompetitive computer circuit netword having no master
JPH0131226B2 (en) * 1980-05-19 1989-06-23 Data General Corp

Also Published As

Publication number Publication date
JPS592942B2 (en) 1984-01-21

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