JPS5372541A - Interruption control system - Google Patents
Interruption control systemInfo
- Publication number
- JPS5372541A JPS5372541A JP14903576A JP14903576A JPS5372541A JP S5372541 A JPS5372541 A JP S5372541A JP 14903576 A JP14903576 A JP 14903576A JP 14903576 A JP14903576 A JP 14903576A JP S5372541 A JPS5372541 A JP S5372541A
- Authority
- JP
- Japan
- Prior art keywords
- control system
- interruption control
- interruption
- control unit
- peripheral control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To delete the interruption signal of each peripheral control unit connected to CPU unit, by putting the interruption signal of each peripheral control unit on the data bus, and thus to carry out an interruption control with simplified interface structure.
COPYRIGHT: (C)1978,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14903576A JPS5372541A (en) | 1976-12-10 | 1976-12-10 | Interruption control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14903576A JPS5372541A (en) | 1976-12-10 | 1976-12-10 | Interruption control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5372541A true JPS5372541A (en) | 1978-06-28 |
Family
ID=15466227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14903576A Pending JPS5372541A (en) | 1976-12-10 | 1976-12-10 | Interruption control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5372541A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5513475A (en) * | 1978-07-14 | 1980-01-30 | Nec Corp | Bus selection system |
JPS5528117A (en) * | 1978-08-15 | 1980-02-28 | Fujitsu Ltd | Interruption indentifying processing system for input and output unit |
JPS55131831A (en) * | 1979-04-02 | 1980-10-14 | Nec Corp | Bus transfer start system |
JPS5676848A (en) * | 1979-11-28 | 1981-06-24 | Burr Brown Res Corp | Control system |
JPS6174144U (en) * | 1980-07-30 | 1986-05-20 | ||
US4648102A (en) * | 1983-03-29 | 1987-03-03 | International Business Machines Corp. | Bus interface device for a data processing system |
US4799148A (en) * | 1984-10-30 | 1989-01-17 | Kabushiki Kaisha Toshiba | Interrupt control system having a processor for determining service priority among a plurality of modules according to an interrupt status table |
JPH01266635A (en) * | 1988-04-19 | 1989-10-24 | Hitachi Ltd | Semiconductor integrated circuit |
US5637237A (en) * | 1994-03-08 | 1997-06-10 | International Business Machines Corporation | Method for hot wall reactive ion etching using a dielectric or metallic liner with temperature control to achieve process stability |
-
1976
- 1976-12-10 JP JP14903576A patent/JPS5372541A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5513475A (en) * | 1978-07-14 | 1980-01-30 | Nec Corp | Bus selection system |
JPS5528117A (en) * | 1978-08-15 | 1980-02-28 | Fujitsu Ltd | Interruption indentifying processing system for input and output unit |
JPS5844251B2 (en) * | 1978-08-15 | 1983-10-01 | 富士通株式会社 | I/O device interrupt identification processing method |
JPS55131831A (en) * | 1979-04-02 | 1980-10-14 | Nec Corp | Bus transfer start system |
JPS5676848A (en) * | 1979-11-28 | 1981-06-24 | Burr Brown Res Corp | Control system |
JPS633348B2 (en) * | 1979-11-28 | 1988-01-22 | Burr Brown Corp | |
JPS6174144U (en) * | 1980-07-30 | 1986-05-20 | ||
US4648102A (en) * | 1983-03-29 | 1987-03-03 | International Business Machines Corp. | Bus interface device for a data processing system |
US4799148A (en) * | 1984-10-30 | 1989-01-17 | Kabushiki Kaisha Toshiba | Interrupt control system having a processor for determining service priority among a plurality of modules according to an interrupt status table |
JPH01266635A (en) * | 1988-04-19 | 1989-10-24 | Hitachi Ltd | Semiconductor integrated circuit |
US5637237A (en) * | 1994-03-08 | 1997-06-10 | International Business Machines Corporation | Method for hot wall reactive ion etching using a dielectric or metallic liner with temperature control to achieve process stability |
US5798016A (en) * | 1994-03-08 | 1998-08-25 | International Business Machines Corporation | Apparatus for hot wall reactive ion etching using a dielectric or metallic liner with temperature control to achieve process stability |
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