JPS5525176A - Memory unit control system - Google Patents

Memory unit control system

Info

Publication number
JPS5525176A
JPS5525176A JP9887178A JP9887178A JPS5525176A JP S5525176 A JPS5525176 A JP S5525176A JP 9887178 A JP9887178 A JP 9887178A JP 9887178 A JP9887178 A JP 9887178A JP S5525176 A JPS5525176 A JP S5525176A
Authority
JP
Japan
Prior art keywords
pages
circuit
access
answer
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9887178A
Other languages
Japanese (ja)
Other versions
JPS5931740B2 (en
Inventor
Tomihide Seo
Tatsuo Ushiki
Tadakazu Morisawa
Shinji Tachika
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP9887178A priority Critical patent/JPS5931740B2/en
Publication of JPS5525176A publication Critical patent/JPS5525176A/en
Publication of JPS5931740B2 publication Critical patent/JPS5931740B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To quicken an overlaying process of a minor switching system, etc., by allowing simultaneous access to several pages when several pages differ in speed.
CONSTITUTION: To memory unit 10 consisting of pages 11 to 14, memory control circuit 20 is connected which has page control circuit 30 and answer signal receiver circuit 40. Then, data bus 21 is connected in common to respective pages 11 to 14 and page access request signal lines 31 to 34 from control circuit 30, and answer signal lines 41 to 44 and page display lines 46 to 49 from circuit 40 are connected to pages 11 to 14. In this constitution, circuit 30 is enable to write the same content to pages 11 to 14 in unit 10 at the same time and circuit 40 is provided with a circuit which receives access answer signals from respective pages 11 to 14 and a circuit which generates an access answer reception end signal on receiving all access answer signals from pages 11 to 14 where access has been attained in a multipage simultaneous access mode, thereby quickening the overlaying process.
COPYRIGHT: (C)1980,JPO&Japio
JP9887178A 1978-08-14 1978-08-14 Storage device control method Expired JPS5931740B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9887178A JPS5931740B2 (en) 1978-08-14 1978-08-14 Storage device control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9887178A JPS5931740B2 (en) 1978-08-14 1978-08-14 Storage device control method

Publications (2)

Publication Number Publication Date
JPS5525176A true JPS5525176A (en) 1980-02-22
JPS5931740B2 JPS5931740B2 (en) 1984-08-03

Family

ID=14231238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9887178A Expired JPS5931740B2 (en) 1978-08-14 1978-08-14 Storage device control method

Country Status (1)

Country Link
JP (1) JPS5931740B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730165A (en) * 1980-07-29 1982-02-18 Fujitsu Ltd Random access memory
US7203809B2 (en) 1994-01-21 2007-04-10 Renesas Technology Corp. Data transfer control method, and peripheral circuit, data processor and processing system for the method

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6166824U (en) * 1984-10-08 1986-05-08
JPH0436011Y2 (en) * 1985-03-05 1992-08-26
JPS62158722U (en) * 1986-03-31 1987-10-08
JPH02110135U (en) * 1989-02-21 1990-09-04

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5730165A (en) * 1980-07-29 1982-02-18 Fujitsu Ltd Random access memory
JPS6232555B2 (en) * 1980-07-29 1987-07-15 Fujitsu Ltd
US7203809B2 (en) 1994-01-21 2007-04-10 Renesas Technology Corp. Data transfer control method, and peripheral circuit, data processor and processing system for the method

Also Published As

Publication number Publication date
JPS5931740B2 (en) 1984-08-03

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