FR2431734A1 - Digital data communication system - allows communication at chosen speed between peripheral couplers and central processing unit - Google Patents

Digital data communication system - allows communication at chosen speed between peripheral couplers and central processing unit

Info

Publication number
FR2431734A1
FR2431734A1 FR7821446A FR7821446A FR2431734A1 FR 2431734 A1 FR2431734 A1 FR 2431734A1 FR 7821446 A FR7821446 A FR 7821446A FR 7821446 A FR7821446 A FR 7821446A FR 2431734 A1 FR2431734 A1 FR 2431734A1
Authority
FR
France
Prior art keywords
processing unit
couplers
memories
microprocessor
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7821446A
Other languages
French (fr)
Other versions
FR2431734B3 (en
Inventor
Claude Borde
Henri Tobiet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Clemessy SA
Original Assignee
Clemessy SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clemessy SA filed Critical Clemessy SA
Priority to FR7821446A priority Critical patent/FR2431734A1/en
Publication of FR2431734A1 publication Critical patent/FR2431734A1/en
Application granted granted Critical
Publication of FR2431734B3 publication Critical patent/FR2431734B3/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Abstract

The equipment comprises a processing unit (UT) communicating with memories (M) and couplers (C1, C2, C3..). The processing unit is connected to memories and to couplers by a bus (BDB). Each coupler and each memory is connected to the processing unit by an interruption line (IT1, IT2..) and an addressing line (N1, N2..). In addition the memories are connected to the processing unit by a bus (EBD) which is an extension of the bus (BDB). The processing unit comprises a microprocessor which is in contact with the memories and couplers. The dialogue between the microprocessor and memories is effected using a write signal and a read signal, while further read and write signals control microprocessor dialogue with the couplers. Communication between the microprocessor and the couplers is so controlled that peripheral couplers are not obliged to carry on a dialogue at a speed determined by the microprocessor.
FR7821446A 1978-07-19 1978-07-19 Digital data communication system - allows communication at chosen speed between peripheral couplers and central processing unit Granted FR2431734A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7821446A FR2431734A1 (en) 1978-07-19 1978-07-19 Digital data communication system - allows communication at chosen speed between peripheral couplers and central processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7821446A FR2431734A1 (en) 1978-07-19 1978-07-19 Digital data communication system - allows communication at chosen speed between peripheral couplers and central processing unit

Publications (2)

Publication Number Publication Date
FR2431734A1 true FR2431734A1 (en) 1980-02-15
FR2431734B3 FR2431734B3 (en) 1981-04-30

Family

ID=9210919

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7821446A Granted FR2431734A1 (en) 1978-07-19 1978-07-19 Digital data communication system - allows communication at chosen speed between peripheral couplers and central processing unit

Country Status (1)

Country Link
FR (1) FR2431734A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0092976A2 (en) * 1982-04-22 1983-11-02 Fanuc Ltd. Memory writing control apparatus
US5978859A (en) * 1994-09-15 1999-11-02 Nokia Telecommunications Oy Implementation of timing between a microprocessor and its peripheral devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0092976A2 (en) * 1982-04-22 1983-11-02 Fanuc Ltd. Memory writing control apparatus
EP0092976A3 (en) * 1982-04-22 1985-08-07 Fanuc Ltd. Memory writing control apparatus
US5978859A (en) * 1994-09-15 1999-11-02 Nokia Telecommunications Oy Implementation of timing between a microprocessor and its peripheral devices

Also Published As

Publication number Publication date
FR2431734B3 (en) 1981-04-30

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