FR2325107A1 - Minicomputer asynchronous memory control system - has several memory module and single toway common lines such that max. data transfer is achieved with min. signalling lines - Google Patents

Minicomputer asynchronous memory control system - has several memory module and single toway common lines such that max. data transfer is achieved with min. signalling lines

Info

Publication number
FR2325107A1
FR2325107A1 FR7620850A FR7620850A FR2325107A1 FR 2325107 A1 FR2325107 A1 FR 2325107A1 FR 7620850 A FR7620850 A FR 7620850A FR 7620850 A FR7620850 A FR 7620850A FR 2325107 A1 FR2325107 A1 FR 2325107A1
Authority
FR
France
Prior art keywords
memory
unit
lines
toway
minicomputer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7620850A
Other languages
French (fr)
Inventor
Frank Kruglinski
Michael Lania
Sami Henig
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DIGITAL COMPUTER CONTROLS
Original Assignee
DIGITAL COMPUTER CONTROLS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DIGITAL COMPUTER CONTROLS filed Critical DIGITAL COMPUTER CONTROLS
Publication of FR2325107A1 publication Critical patent/FR2325107A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

The asynchronous memory system has a memory unit and a memory control associated with the memory unit. Receiving means in the memory control, receive mode control signals emanating from a unit external to the memory. There signals indicate the reading, writing and increase/decrease modes of operation. The memory system has means for producing a memory signal in response to each of the mode control signals. A single path is used for transmission of all the control signals from the memory control to the unit external to the memory. The system includes several memory controls each associated with a memory unit. The external unit is a central data processor or a data channel. The memory signal is a first transition from a lower to an upper voltage level, which indicates recognition of reception of mode control signals.
FR7620850A 1975-07-08 1976-07-08 Minicomputer asynchronous memory control system - has several memory module and single toway common lines such that max. data transfer is achieved with min. signalling lines Withdrawn FR2325107A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US59395375A 1975-07-08 1975-07-08

Publications (1)

Publication Number Publication Date
FR2325107A1 true FR2325107A1 (en) 1977-04-15

Family

ID=24376905

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7620850A Withdrawn FR2325107A1 (en) 1975-07-08 1976-07-08 Minicomputer asynchronous memory control system - has several memory module and single toway common lines such that max. data transfer is achieved with min. signalling lines

Country Status (4)

Country Link
JP (1) JPS5255834A (en)
CA (1) CA1062376A (en)
DE (1) DE2630711A1 (en)
FR (1) FR2325107A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2404878A1 (en) * 1977-09-30 1979-04-27 Siemens Ag ASSEMBLY FOR INTERRUPTION INSTRUCTION ENTRY AND INTERRUPTION ACKNOWLEDGMENT RELEASE FOR COMPUTER SYSTEMS
FR2425184A1 (en) * 1978-05-05 1979-11-30 Hisi Spa BIDIRECTIONAL TRAP SIGNAL TRANSMISSION SYSTEM
FR2511790A1 (en) * 1981-08-24 1983-02-25 Sony Corp DATA TRANSFER APPARATUS FOR A MICROCALCULATOR DEVICE
EP0258873A2 (en) * 1986-09-01 1988-03-09 Nec Corporation Serial bus interface system for data communication using two-wire line as clock bus and data bus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NO002867 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2404878A1 (en) * 1977-09-30 1979-04-27 Siemens Ag ASSEMBLY FOR INTERRUPTION INSTRUCTION ENTRY AND INTERRUPTION ACKNOWLEDGMENT RELEASE FOR COMPUTER SYSTEMS
FR2425184A1 (en) * 1978-05-05 1979-11-30 Hisi Spa BIDIRECTIONAL TRAP SIGNAL TRANSMISSION SYSTEM
FR2511790A1 (en) * 1981-08-24 1983-02-25 Sony Corp DATA TRANSFER APPARATUS FOR A MICROCALCULATOR DEVICE
EP0258873A2 (en) * 1986-09-01 1988-03-09 Nec Corporation Serial bus interface system for data communication using two-wire line as clock bus and data bus
EP0258873A3 (en) * 1986-09-01 1989-11-02 Nec Corporation Serial bus interface system for data communication usingserial bus interface system for data communication using two-wire line as clock bus and data bus two-wire line as clock bus and data bus

Also Published As

Publication number Publication date
JPS5255834A (en) 1977-05-07
CA1062376A (en) 1979-09-11
DE2630711A1 (en) 1977-10-06

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Legal Events

Date Code Title Description
ST Notification of lapse