JPS57184354A - Digital transmitter - Google Patents
Digital transmitterInfo
- Publication number
- JPS57184354A JPS57184354A JP56068216A JP6821681A JPS57184354A JP S57184354 A JPS57184354 A JP S57184354A JP 56068216 A JP56068216 A JP 56068216A JP 6821681 A JP6821681 A JP 6821681A JP S57184354 A JPS57184354 A JP S57184354A
- Authority
- JP
- Japan
- Prior art keywords
- information
- circuit
- transmitting
- buffer memory
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
Abstract
PURPOSE:To ensure a certain value for the delay time of transmission of information from the input of a transmitting buffer memory device through the output of a receiving buffer memory device, by periodically setting the transmitting speed of information at a constant level for a cerfain period of time at a transmitting part. CONSTITUTION:The TV signal supplied to a coding device 11 is transmitted to a multiplexing circuit 12 through a transmitting part and written into a transmitting buffer memory 13. A dummy adding circuit 14, when detecting a specific pattern whose transmission is inhibited in the information read out of the memory 13, inserts the dummy data into the block. The circuit 14 also inserts the dummy data when the fixing of the transmitting speed is requested by an information transmitting speed control circuit 15. At the receiving part, the transmitted information is fed to a dummy eliminating circuit 16 and then written into a receiving buffer memory 17. Then a separating circuit 18 reads the information out of the memory 17 based on a command given from an information storage quantity monitor circuit 20 and sends it to a decoding device 19.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56068216A JPS57184354A (en) | 1981-05-08 | 1981-05-08 | Digital transmitter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56068216A JPS57184354A (en) | 1981-05-08 | 1981-05-08 | Digital transmitter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57184354A true JPS57184354A (en) | 1982-11-13 |
JPS6325730B2 JPS6325730B2 (en) | 1988-05-26 |
Family
ID=13367375
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56068216A Granted JPS57184354A (en) | 1981-05-08 | 1981-05-08 | Digital transmitter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57184354A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0431319A2 (en) * | 1989-11-06 | 1991-06-12 | Fujitsu Limited | Video signal coding apparatus, coding method and video signal coding transmission system |
JP2012054847A (en) * | 2010-09-03 | 2012-03-15 | Nec Access Technica Ltd | Device and method for clock regeneration, and control program |
-
1981
- 1981-05-08 JP JP56068216A patent/JPS57184354A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0431319A2 (en) * | 1989-11-06 | 1991-06-12 | Fujitsu Limited | Video signal coding apparatus, coding method and video signal coding transmission system |
JP2012054847A (en) * | 2010-09-03 | 2012-03-15 | Nec Access Technica Ltd | Device and method for clock regeneration, and control program |
Also Published As
Publication number | Publication date |
---|---|
JPS6325730B2 (en) | 1988-05-26 |
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