GB1479313A - Digital data rate converters - Google Patents

Abstract

1479313 Data transmission; speed changing MARCONI CO Ltd 26 March 1975 [2 April 1974] 14529/74 Heading H4P A bit rate converter for transmitting data at a rate higher than incoming comprises means dividing lower bit rate incoming data into determined word length which are stored then read-out at a higher rate and means for detecting the difference in rates and inserting padding words of fixed length into the output stream such that the padding words fill the gaps. The higher rate may be independent of the lower and data word length may be the same as the padding word, which can contain information regarding the position of the next following padding word. 60 kHz bipolar data applied at terminal 2 is converted to binary form by converter 1 which also synchronizes oscillator 3; this drives serial/parallel converter 4 dividing the data into 8 bit words, also word counter 6 through a ¸8 dividing circuit 5. Counter 6 outputs specify the next location of a store 7 to be filled, content of which is monitored by 8, also recording clock rates. Parallel/serial converter 10 is driven at a transmitting frequency of 64 kHz causing data words to be read-out of store 7 at this higher rate which is also detected by 8 from which difference in rates is determined. When a counter 15, clocked at word rate 8 kHz is full, it is reset and an enabling signal passed to padding word generator 16, selector 9 and counter 14; the word developed by 16 depends on an input from 8 which specifies for example whether the next padding word will be found after 14, 15 or 16 information words, counter 15 being given a start position depending on the number of words. At insertion periods counter 14 is inhibited for one word. If input and output clocks are in relative synchronism, content of store 7 will remain substantially constant hence generator 16 may produce a coded signal of 0001 to counter 15 hence provide a reset signal after 15 words have been transmitted. If the transmitting clock is running relatively slowly, store 7 will tend to fill hence the signal passed to counter 15 will be 0000 hence will reset every 16 words. Conversely if store 7 is tending to empty then 0010 is passed to 15 hence insertion will be after only 14 words. The receiver, which is approximately a "mirror image" of a transmitter has a counter (26), Fig. 2 (not shown), receiving the coded signal specifying the position of the next padding word and provides on reset this information to a device (24) which arrangement avoids error in case an information word should fortuitously contain the same sequence as padding words. The receiver also includes a frequency control (31) thus ensuring that store (23) neither completely fills nor empties.