JPS56109091A - Time slot replacing system - Google Patents

Time slot replacing system

Info

Publication number
JPS56109091A
JPS56109091A JP1122380A JP1122380A JPS56109091A JP S56109091 A JPS56109091 A JP S56109091A JP 1122380 A JP1122380 A JP 1122380A JP 1122380 A JP1122380 A JP 1122380A JP S56109091 A JPS56109091 A JP S56109091A
Authority
JP
Japan
Prior art keywords
time
bit
address
memory
time slot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1122380A
Other languages
Japanese (ja)
Other versions
JPS6219120B2 (en
Inventor
Yuji Kubota
Kuniaki Kihara
Takeshi Kakino
Masaki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1122380A priority Critical patent/JPS56109091A/en
Publication of JPS56109091A publication Critical patent/JPS56109091A/en
Publication of JPS6219120B2 publication Critical patent/JPS6219120B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To enable to change the content of a time slot conversion memory without interruption of time slot replacing operation, by the address replacement at the time of D0-D5 bit and F, S bit-time of input signals. CONSTITUTION:The serial data signal given to input terminals 1-1-1-N is in time sharing and multiplex each bit, and it is converted into parallel data every channel and written in the buffer memory 3 at the time of F-bit. The parallel data signal read out from the buffer memory 3 is written in the buffer memory 5 with the address N of the converted address read out at D0-D5 bit time from the time slot conversion memory 13. The content of the memory 5 is stored in the same address of the parallel serial conversion buffer memory 5-2 with the address of the address generating circuit 10 at the S-bit time. The content of the memory 5-1 is read out as the multiplex serial data signal and output as the serial data signal through separation.
JP1122380A 1980-02-01 1980-02-01 Time slot replacing system Granted JPS56109091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1122380A JPS56109091A (en) 1980-02-01 1980-02-01 Time slot replacing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1122380A JPS56109091A (en) 1980-02-01 1980-02-01 Time slot replacing system

Publications (2)

Publication Number Publication Date
JPS56109091A true JPS56109091A (en) 1981-08-29
JPS6219120B2 JPS6219120B2 (en) 1987-04-27

Family

ID=11771955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1122380A Granted JPS56109091A (en) 1980-02-01 1980-02-01 Time slot replacing system

Country Status (1)

Country Link
JP (1) JPS56109091A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5944192A (en) * 1982-09-06 1984-03-12 Fujitsu Ltd Address converting system of channel memory
JPS61198939A (en) * 1985-02-28 1986-09-03 Oki Electric Ind Co Ltd Multiplex converting circuit
CN107391422A (en) * 2017-07-19 2017-11-24 上海航天测控通信研究所 multi-path asynchronous serial communication data access system and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53122301A (en) * 1977-03-31 1978-10-25 Murata Manufacturing Co Television tuner

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53122301A (en) * 1977-03-31 1978-10-25 Murata Manufacturing Co Television tuner

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5944192A (en) * 1982-09-06 1984-03-12 Fujitsu Ltd Address converting system of channel memory
JPH0129353B2 (en) * 1982-09-06 1989-06-09 Fujitsu Ltd
JPS61198939A (en) * 1985-02-28 1986-09-03 Oki Electric Ind Co Ltd Multiplex converting circuit
CN107391422A (en) * 2017-07-19 2017-11-24 上海航天测控通信研究所 multi-path asynchronous serial communication data access system and method

Also Published As

Publication number Publication date
JPS6219120B2 (en) 1987-04-27

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