GB1494830A - Resynchronising system for multiplexed pulse code modulation signals - Google Patents

Abstract

1494830 Time division multiplex systems A ROCHE 27 Dec 1974 [27 Dec 1973] 55920/74 Heading H4M In an arrangement for synchronizing digital time multiplexed signals received in accordance with a distant clock with a multiplex system operating in accordance with an independent local clock, the received signals are, as in the prior art, first fed into an input register 1 at the distant clock rate, which is reconstituted by a conventional flywheel circuit 2, and thence into a buffer register 3, whose capacity is that of a single time slot. At instants defined by a transfer control circuit 5, the contents of the buffer register are written in to the frame memory 4, at addresses defined by the reconstituted clock. The frame memory is read out from these addresses at instants defined by the local clock 7. It is necessary to time matters such that read out from the buffer 3 is subsequent to write in, and as the two clocks shift with respect to one another, it is necessary periodically to change the instant in the local clock at which the buffer 3 is read, e.g. from the second to the sixth bits in a time slot, or vice versa. In the prior art, this is done by comparing a reference pulse in each time slot of the distant clock with two "time windows" in the time slot of the local clock in a comparator 6. As the distant reference pulse enters the window around the instant currently in use for read out, logic arrangements in the transfer control circuit 5 operate to select the other instant for read out in the following time slot. This results in either duplication or omission of a time slot in the transfer to the frame memory, depending on whether the distant clock is slower or faster than the local clock. To avoid this difficulty, in the present invention, the logic arrangements are modified such that if switching from the earlier read out instant to the later is necessary in conditions where a time slot would be omitted, this occurs during the same time slot during which coincidence in the window occurred, rather than in the succeeding one. In the embodiment shown in Fig. 4, a signal indicating that the distant reference is in the second time window (f 1 <SP>1</SP>, f 2 <SP>1</SP>) is delivered to AND gate 511, a signal indicating that the reference is in the first half of the first window is delivered to AND gate 516 and a signal indicating that the reference is in the second half f 2 of the first window is delivered to AND gate 517. Gates 511 and 516 receive signals from the first bit of the local clock W 0 , so that coincidence on these gates will switch flip-flop 510 to select at gates 513 or 514 the appropriate read out instant C 1 or C 2 , which will be in the following time slot, W 0 being the first bit in that slot. Gate 517 however receives the fifth bit of the time slot, so that coincidence on this gate results in the flip-flop 510 switching during the middle of the current time slot. There will still be a jump in reading out the addresses of the frame memory 4 and to avoid loss of information due to this, it may be arranged, Fig. 5, not shown, that one of the time slots (W 0 ) of the distant frame contains stuffing bits, which can be detected by appropriately coding the most significant bit, and the results of this detection used to control the gates referred to above, such that the change of read out instants for the buffer 3 (write in to frame memory 4) only occurs during stuffing time slots. Loss or duplication of such a time slot in reading out the memory 4 does not result in loss of information. Once in 32 frames the above arrangements result in a jump of a whole frame. This can be obviated by reading out the frame memory using in succession each alternate time slot. This is achieved by including a permutation circuit and address comparator in association with the address multiplexer and the logic arrangements, such that the change of read out occurs only during stuffing time slots (Fig. 7, not shown).