SU1434495A1 - Device for forming addresses of buffer storage - Google Patents

Abstract

The invention relates to computing and is used in blocks of buffer memory. The purpose of the invention is to expand the scope by forming current addresses for specified areas of the buffer memory. The device contains memory block 1, arithmetic logic unit 2, register 3, element 4, first 5 and second 6 counters, driver 7, adder 8, multiplexer 9. The device is intended to form addresses for the buffer memory of data transceivers connection with the temporary sealing of the channels. The time-multiplexed path is two lines — a line of transmitted data and a line of received data, through which information is transmitted and received on several channels, respectively. In each channel slot, one data word is transmitted or received. 3 il. G (L with

Description

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The invention relates to computing and can be used in blocks of buffer memory.

The purpose of the invention is to expand the scope by forming the current addresses of specified areas of the buffer memory.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagram of the device; in fig. 3 shows an example of the state of a device in the process of receiving and transmitting messages.

The device for generating addresses of the buffer memory (Fig. 1) contains a memory block 1, an arithmetic logic unit (ALB) 2, register 3, element 4, first 5, second 6 counters shaper 7 reset signals, adder 8, multiplexer 9, the first and second inputs 10 and 1 of the synchronizer, the input 12 of the load, the input 13 of the read record, the first and second ports 14 and 15 of resolution, the first and second address inputs 16 and 17, the output 18 of the counter 5, the output 19 of the memory block 1, output 20 of the counter 6, the output 21 of the driver 7.

The first device sync input (input 10) is the channel synchronization input and is intended to synchronize the time slots. By the 1-0 difference of the channel synchronization signal, the state of the slot interval counter (counter 6) changes by one. ,

The second device sync input (input 11) is a frame synchronization input and is intended to synchronize the zero time slot. The differential 0-1 of the frame alignment signal. The shaper 7 generates a reset signal (FIG. 2) of the channel interval counter (counter 6

The device load input (input 12) provides loading from output 2 to register 3 to receive the current address for the current channel at device output 16 (first for receiving, then for transmitting). The input of the read record of the device (input 13) is intended to strob write to memory block 1 depending on the state of the enable inputs: from the state of the first enable input (input 14) in the receive cycle and the second enable input (input 15) in the cycle transfer. The input signal is selected by the multiplexer 9.

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Counter 6 is determined from a cycle of channel intervals of the path with a temporary seal. Dp 32 ka kalov counter size is 3.

The length of the counter 5 is determined by the maximum message length on one of the channels. At maximum

Q is the length of a message of eight words, the counter 5, as well as the block 1 of memory, has a width of three.

Counter 5 is designed to form a current count for the five 15 AAB 2 current addresses. Memory unit 1 is designed to record and store D.Li counts for each transmitter and each receive channel. With the number of channels 32, the capacity of memory block 1

20 is 64 words, the word depth depending on the maximum message length. The current address is formed by ALB 2, which performs onepaijjiro C - B - 1, where C 25 is the state of output 18 of counter 5 (the current count); B - state of state 19 block 1 of memory. Counter 6 generates the channel slot number (address of the buffer memory area). Sum30 torus 8 is designed to match the input and output information received and transmitted from the buffer memory. In the reception cycles of the state of the counter 6, the adder 8 decreases by 1,

OS in the transmission cycle increases by 1.

Each channel interval is divided into four cycles of accessing memory block 1: read, write, read, write. The first two calls were received when the message was received, the second two calls were sent when sending a message.

In the initial state, in the write cycles in the memory block 1, the value of the counter 5 is continuously recorded. Pulse d5 of the record passes through the element 4 to the input of the record of the memory block 1.

In read cycles from memory block 1, the value written to memory block 1 in the same channel interval of the previous cycle is read. As a result, for all channels at the output of the ADF 2, code zero is generated and loaded into register 3 — the initial current addresses for each channel of both the receiver and the transmitting channel, as in this case, B C - 1.

When a message word arrives, what the logical O indicates in the receive loop at input 14 of the device, 50

55

no more (in the corresponding channel interval) write to memory block 1. Thus, for the given channel interval over which the message passes, in block 1 of memory at the corresponding address, equal to the channel interval number, the value C, preceding the appearance of the signal at input 14, will be recorded. The output of memory block 1 in the corresponding slot will increase by 1, which is explained by a constant value B for a given channel interval, due to the prohibition of recording and a change in value C at the beginning of each cycle. Thus, at the device input 16, a current address is formed for the corresponding channel interval.

A message is a sequence of words of messages that cause an O to occur at input 14

Mr. interval. The occurrence of the message word in the zero channel (O on input 14) causes the prohibition of writing to memory block 1, as a result of which the state of output 19 of memory 1 does not change in this slot, and the state of output 16 of the device increases by 1 because Output 18 continues to increase.

In the transmission cycle, the operation of the device differs only in that the ratio is informed by a signal at the input 15.

Claims (1)

Invention Formula A device for generating addresses of the buffer memory comprising a memory block, a multiplexer, a register and an AND element, the register output being the first device address output, the register loading input being the device loading input, the first thirty 35 the device for the received and the input pi, the address input of the memory block is de 15 for the transmitted message in the first synchronization input of the device corresponding to the channel interval. The words that are displayed in the corresponding message word in the corresponding channel interval are called record by the corresponding address of the current reference memory block 1, i.e. initialization of the current address. When transmitting messages in transmission cycles, the state of input 15 is analyzed. In FIG. 3 shows an example of the state of a device in the process of receiving and transmitting a message. The device counter 5 is not initialized and constantly each cycle changes its state (output 18). At the output 20 of the counter 6, channel interval inputs are formed. At the output 17 of the adder 8, we have reduced the slot interval code and reception cycles (in order to match the input information delay, since the input data word will be fully received at the end of this channel interval) and increased by 1 channel interval code in transmission cycles (since the word this channel interval will be transmitted with a delay of one channel interval). If there is no message word at the input (1 at the device input 14) 40 45 50 In order to expand the scope of application by forming current addresses for specified areas of the buffer parameter, the arithmetic logic unit, the first and second counters, the adder, the shaper of reset signals, and the synchronization input are entered into it. the first counter is connected to the input of the signal conditioner, reset, and is the second synchronization input of the device; the output of the reset signal generator is connected to the installation input of the second counter, the outputs of which are connected to the inputs of the first group of sum the second g input; whose rouses are connected to the first sync input of the device and the sync input of the second counter, the outputs of the adder are connected to the address inputs of the memory unit group and are the second address output of the device, the first sync input of the device is connected to the control input multiplexer, the first and second information inputs of which are the first and second inputs of the device operation resolution, the multiplexer output is connected to the second input of the AND element, the first Writing into the block whose input is the recording input / 1 of the state memory of the counter 5 is valid. The device output, the output of the element I Tat of operation ALU 2, at the output 16 of the device, the zero code in each channel is connected to the write / read input memory block, information inputs 0 five i, the address input of the memory block is the first sync input of the device, characterized by 0 five 0 In order to expand the scope of application by forming current addresses for specified areas of the buffer parameter, the arithmetic logic unit, the first and second counters, the adder, the shaper of reset signals, and the synchronization input are entered into it. the first counter is connected to the input of the signal conditioner, reset, and is the second synchronization input of the device; the output of the reset signal generator is connected to the installation input of the second counter, the outputs of which are connected to the inputs of the first group of sum the second g input; whose rouses are connected to the first synchronization input of the device and the sync input of the second counter, the outputs of the adder are connected to the address inputs of the memory block group and are the second address output of the device, the first synchronization input of the device is connected to the multiplexer control input , the first and second information inputs of which are the first and second inputs of the device operation resolution, the multiplexer output is connected to the second input of the AND element, the first which input is the write / read input of the device, the output element And connected to the write / read input of the memory unit, the information inputs of which are 514344956 connected to the outputs of the first counter; connected to the outputs of the block ka and information inputs of the first group of the arithmetic logic unit, information inputs of the second group Memories, outputs of the arithmetic logic unit are connected to the information inputs of the register. // ten go -J-l GP njHJlJlJlJlJ JTnJlJT. „JlJTrLTLTL  ShIIlIPIL lmJL JJLLIII channel o 11 21 Ji    fiepeQQf / ff npueff nepeggt / a - П П П, ПП P Reading conceived i msHus a record which is connected to the outputs of the block memory, outputs of arithmetic logic unit. connected to the information inputs of the register. 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