SU1262510A1 - Interface for linking the using equipment with communication channels - Google Patents

Abstract

The invention relates to computing and can be used in digital communication systems and data processing systems. The aim of the invention is to increase the transmittance due to the simultaneous exchange of information between several pairs of subscribers. The device contains two blocks of transmitters, a block of receivers, an address decoder, an exchange unit, two switches, two registers, two buffer memories, a block of counters, a command decoder, an address and control register. I zp f-ly, 3 ill.

Description

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The invention relates to computing and can be used in digital communication systems and data processing systems.

The purpose of the invention is to increase throughput due to the simultaneous exchange of information between several pairs of subscribers.

FIG. 1 shows a block diagram of a device for interfacing subscribers with communication channels; in fig. 2 - block diagram of the meter; in fig. 3 is a block exchange diagram. The device for interfacing subscribers with communication channels contains a register of 1 address and control, a decoder of 2 commands, a block of 3 counters, a first switch 4, a second 5 and a first 6 buffer memory, a first 7 and a second 8 registers, a second switch 9, the first block 10 transmitters, a block of 11 receivers, a second block of 12 transmitters, a decoder 13 of the address, as well as a block of 14 exchange.

FIG. 1 also denotes an address group of inputs 15, a group of inputs 16 of code conditions, an input 17 of synchronization, a group of code inputs 18, a linear input 19, a group of information inputs 20, a group of address outputs 21, a group of outputs 22 of code conditions, a linear output 23 and a group of information outputs 24

Block 3 counters (Fig. 2) contains the item and 25, the first counter 26, the first key 27, the second key 28, the second counter 29 and the third counter, 30.

Block 14 of the exchange (Fig. 3) contains the first 31, second 32, third 33 and fourth 34 elements And element NO 35, the first 36 and second 37 one-shot, as well as the amplifier-transmitter 38.

The outputs 21, 22 and 24, as well as the inputs 15, 16 and 20 of the device are connected to a common computer mainline.

The device works as follows.

The computer periodically reads the contents of register 7, for which the input code 15 of the computer device provides the address code and control information. The address decoder 13 generates a signal on which the outputs of register 7 through the second switch 9 and the first transmitter unit 10 are connected to a group of information outputs 24. Next, the computer analyzes the received information to make a connection between two subscribers. After that, the register 1 of the address and control of the computer through the receiver unit 11 records the control command and the address of the subscriber unit with which communication is established. The decoder 2 command controls the operation of the block of 3 counters, which clocks registers 7 and 8, made in the form of serial-parallel registers, as well as buffer memories 5 and 6. Depending on the code of the control command, which is stored in register 1 of the address and control, the first switch switches the output of the second register 8 or one of the group of code inputs 18 to the line output 23 of the device. Information from the subscriber arrives at the line input 19 of the device in a serial code, is converted by the first register 7 into a parallel code, and is written into the second buffer memory 5. After it is filled, the counter block 3 outputs to the exchange block 14 a common trunk capture signal in accordance with the arbitration procedure. When the enable signal arrives at the device input 16, the exchange unit 14 outputs to the first 10 and second 12 blocks of transmitters the output signals to the common highway of the content address part of the register 1 and the address and control, as well as the second buffer memory 5.

The address 13 decryptor analyzes the code

Addresses and control information received at the address group of inputs 15 of the device. If the information is addressed to this device, then the control signals are generated at the outputs of the decimator 13. When a read code arrives at the input of the decoder 13 from the first block of 10 transmitters, the contents of the first register 7 are sent to the computer using the algorithm discussed earlier. On admission to

The address inputs 15 of the write code, the decoder 13, sends to the exchange unit 14 a signal on which this unit 14 outputs to the common line a confirmation signal for the transmitting subscriber unit and a recording signal for the block 3 counters. Using these signals, the block 3 of the counters records the information word from the information input 20 into the first buffer memory 6. When it arrives at the decryptor 13 of the address and command entry code it sends the control signals to the exchange unit 14 and you

working on acknowledgment signals

and readout for the transmitting subscriber unit and register 1. By writing to the address and control register via the receiver unit 11, information is input to the information input 20 of the device.

Block 3 counters works as follows.

The signal from the decoder 2 commands to the input of block 3, allows passing through the element And 25 signals of the clock frequency fo from the synchronization input 17 to the first counter 26 and switches the counters 26, 29 and 30 into the counting mode. Counter 26 operates as a frequency divider fo on K, where K is

Claims (2)

word size. Depending on the control signals on the third inputs of the keys 27 and 28, the latter pass to the first inputs of the second 29 and third 30 counters the signals from the first counter 26, or the signals from the third and fourth outputs of block 3. The order of filling the buffer memories 5 and 6 is determined the state of the bits of the second 29 and third 30 counters of block 3, respectively. The second counter 29 controls the recording of information words in the second buffer memory 5 and counts the write pulses from the first counter 26. After filling the second buffer memory 5, the counter 25 batyvaet overflow signal, which is supplied via output overflow counter unit 3 in the exchange unit 14 switches the first switch 27 to receiving acknowledgment pulses words from the exchange unit 14 and a second buffer memory 5 in the readout mode. The third counter 30 controls the recording of information words from the transmitting subscriber unit to the first buffer memory 6. It receives, via the second key 28, word synchronization signals from the exchange unit 14. After the first buffer memory 6 is filled, the switch signal switches the key 28 to receive pulses from the first counter 26 and switches memory 6 to the read mode of words in register 8. After reading the words from memory 6, the overflow signals are blocked and the device is ready to receive the next information from transmitting subscriber device. The exchange unit 14 operates as follows. When addressing information to the (proposed) device, a potential appears at the input of the second element 32. This allows the synchronization signal to pass through to the second one-shot 37. The latter generates a write signal for the block of 3 counters and 1 register of the address and control, as well as a small delay acknowledgment of receipt of information. When the device is currently in the transmission mode, what happens when the information words overflow the second buffer memory 5, the overflow signal is fed to the information input of the exchange unit 14 and then to the amplifier 38, the fourth element 34 and the element NOT 35. With the arrival the overflow signal of the third element And 33 generates a transmission request signal. After the resolution signal arrives at block 14 at the output of the fourth element 34, a signal is generated which opens the first element 31 (for confirmation signals), the first transmitter unit 10 and the second transmitter unit 12 (via the resolution output of the exchange unit 14). With the same signal, the first one-shot 36 with some delay produces at the output 22 of the control of the device a synchronization pulse of the word output to the common line. Claim 1. Device for interfacing subscribers with communication channels, comprising two transmitter units, a receiver unit, an address decoder, an exchange unit, the groups of information outputs of the first and second transmitter blocks are connected to groups of information and address subscribers, respectively, the group of information inputs of the receiver unit is connected to the group of information outputs of subscribers, the group of information inputs of the address decoder is connected to the group of address outputs of subscribers, the information group x inputs and outputs of the exchange unit are connected to groups of inputs and outputs of subscriber logical conditions, while the first output of the address decoder is connected to the enabling input of the exchange unit, allowing the output of which is connected to the enabling inputs of the first and second blocks of transmitters, in order to increase bandwidth due to the simultaneous exchange of information between several pairs of subscribers, two switches, two buffer memories, two registers, a command decoder, a block of counters, a register are entered into it address and control, where the information input of the first register is connected to the output of the communication channel, the output of the first switch is connected to the input of the communication channel, the synchronous input of the meter block is the synchronous input of the device, and the group of information inputs of the first transmitter block is connected to the group of information outputs of the second switch whose control input is connected to the second output of the address decoder, the third output of which is connected to the write input of the address register and control, whose read input is connected to input the record unit's write house and the write output of the exchange unit, the clock output of which is connected to the counter input of the counter block, the overflow output of which is connected to the information input of the exchange unit, the group of information inputs of the second transmitter unit is connected to the first group of information outputs of the address and control register, the group of information whose inputs are connected to the group of information outputs of the receiver unit and to the group of information inputs of the first buffer memory, the group of information outputs of which It is connected to the group of information inputs of the second register, the information output of which is connected to the information input of the first switch, the group of control inputs of which is connected to the second group of information outputs of the address and control register and the group of information inputs of the command decoder, the group of outputs which is connected to the group of information inputs a block of meters whose output is connected to the synchronous inputs of the first and second registers, the group of information outputs of the first register is connected to a group information inputs of the second buffer memory and the first group of information inputs of the second switch, the second group of information inputs of which are connected to the group of information outputs of the second buffer memory, the group of recording entries of which are connected with the first group of bit outputs of the counter block, the second group of bit outputs connected to a group of inputs of the first buffer memory. 2. The device according to claim 1, characterized in that the exchange unit contains four elements AND, the element NOT, an amplifier-transmitter, two single-oscillators, the first inputs of the first, second and third elements AND form the group of information inputs of the exchange unit, the first outputs of the first and second one-shot, outputs third element AND and amplifier-transmitter form a group of information outputs of the exchange unit, input of the amplifier-transmitter is connected to the input of the element NOT, with the first input of the fourth element AND, and is the information input of the exchange unit, the second input of the second element AND is the enable input of the exchange unit, output the fourth element And is connected to the first input of the launch of the first one-shot, with the second input of the first element And is the enable output of the exchange unit, the second outputs of the first and second one-shot are clock in The output and output of the exchange unit, respectively, while in the exchange unit, the output of the element is NOT connected to the second input of the third element And, the first input of which is connected to the second input of the fourth element And, the outputs of the first and second elements And is connected to the second input of the first one-shot and one the start input of the second one-shot, respectively. figure 1 Figg