SU1557566A1 - Device for data exchange between information source and receiver - Google Patents

Abstract

The invention relates to computing and can be used in local networks for collecting and processing large arrays of measurement information from various objects. The purpose of the invention is to increase the capacity and performance of the system. The device contains M information output blocks, a group of information input blocks, a control block, a memory block, an address generation priority block, a data selection block. 3 hp f-ly, 9 ill., 1 tab.

Description

The invention relates to computing and can be used in local networks for collecting and processing large arrays of measurement information, measurement information systems for collecting information from various objects, including multiplexed channels of information exchange and its registration on several carriers or simultaneous input. in a number of calculators for further processing.

The aim of the invention is to improve the performance and throughput of the system.

Figure 1 shows the structural diagram of the proposed device; figure 2 is a functional diagram of the block selection data; FIG. 3 is a functional diagram of an address generation priority block; 4 is a functional block diagram of the control unit;

figure 5 is a functional diagram of the input information; Fig. 6 is a functional block diagram of the memory block; Fig. 7 is an example of a variant of a specific implementation of the information input block; Fig. 8 and 9 are timing diagrams of operation of the data selection block and the priority address generation block, respectively.

The device contains (Fig. 1) M information output units 1, a group of information input units 2, a memory unit 3, a control unit 4, a data selection unit 5, an address generation unit 6, an output group 7 and an input group 8.

Data selection block 5 contains (FIG. 2) decoder 9, elements AND 10-12, buffer register 13, shift register 14, one-shot 15-17, trigger 18, switch 19, decoder 20, trigger 21, delay elements 22 and 23 & $

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ki, information output 24 blocks and input 25 of the write request.

Priority address generation unit 6 contains elements 26 and 27 of comparison, elements K 28 - 34, triggers 35 - 38, counters 39 and 40, multiplexer 41, element OR 42, pulse generator 43, elements 44-46 of delay, outputs 47 - 49, the input 50, the input 51 of the read request (FIG. 3).

Control unit 4 contains (FIG. 4) delay elements 52 and 53, control code register 54, memory node 55, address counter 56, AND 57, generator 58, output 59. Information output block 1 contains (FIG. 5) comparison element 60, elements 61 and 62, register 63, signal generator 64, delay element 65, input 66, memory block 3 (6) register 67, memory 68, delay element 69, and element 70.

The information input unit 2 contains (Fig. 7) a group of counters 71 for generating measurement parameters, a timer 72, delay elements 73 and 74, a group of static registers 75 for storing measuring parameters, a multiplexer 76, a comparison element 77, a counter 78, elements 79 and 80

The data selection block 5 serves for receiving and identifying information intended for storing it in block 3, followed by delivery to the consumer. Block 5 receives information and ensures that only those data arrays whose attributes are specified are received. The decoder 9 converts the input phase-manipulated code into a serial binary code with the formation of features of command and information words and synchronization signals. The shift register 14 provides the reception of a sequential code information or command words. The buffer register 13 is designed to store command and information words that are overwritten into it after completion of their formation in register 14. Single-oscillators 15-17 serve to generate single pulses from the control signals of the decoder 9. The trigger 21 is designed to memorize the command sign received from the decoder 9 or information word. The decoder 20 is designed to decrypt the code of the part of the control word in which it is written

sign of the array defined by this command word. The switch 19 serves to generate a data entry enable signal, the feature of which is set in block 5. The setting of the feature of the array to be received is provided by setting 1 for the corresponding decoder output 20. Setting O ensures that input of the data is prohibited. The trigger 18 serves to memorize the attribute of the array from the switch 19 to the time of transmission of the array of data belonging to

“; this command word. The flip-flop 18 is reset by the one-shot 16 signal from the sign of each control word, and the flip-flop 18 is set at input C c

Q output element And 12 according to the coincidence of the characteristic of the control word and the signal from the output of the one-shot 15, delayed by the element 22 of the delay. Trigger 18 is not set,

5 if this array is not allowed to be received into the system. Element 11 is designed to form a request to write command and information words after entering them into the buffer register 13. This signal is generated from a single-shot 15 pulse delayed by delay elements 22 and 23 at resolution from trigger 18. The block diagram of operation 5 is shown in Fig.8.

The priority address generation unit 6 serves to control the processes of combining the recording and reading of information and organizes data buffering in a floating memory space. Block 6 receives the Signal Request and Read Request signals, generates and issues the corresponding write and read addresses in Block 3, with the priority given to reading the data. The trigger 36 serves to memorize the write request from the data selection block 5. A trigger 35 is designed to memorize a read request from control unit 4. Comparison element 26 is needed to form a permission to access block 6 when reading information. Element AND 30 provides the signal flow. Read request to the installation input of the trigger 35 according to the resolution5 of the comparison element 26. Comparison element 26 and element K 30 form the code selector of block 6. Trigger 37 serves to form

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A write-read signal arriving at block 47 output and for controlling multiplexer A1. A trigger 38 organizes reading of data from memory block 3. The installation of the flip-flops 37 and 38 is carried out through the And 32 and 33 elements by spaced pulses from the output of the delay element 44. When triggers 35 and 36 are both set to one, then trigger 37 will be

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first set to one and element 33 will be blocked. Therefore, overwriting the write request signal from trigger 36 to trigger 38 will not occur. Thus, the information reading mode from block 3 will be executed first. Counter 40 is designed to form reading addresses by adding one at the same time as setting trigger 37. Counter 39 is designed to generate write addresses by adding one at the same time as setting trigger 381 Multiplexer 41 serves to multiplex addresses read and write when organizing the appropriate modes. Comparison element 27 is intended to determine when the memory address is finished reading. The end of the reading of the memory is determined by the equality of the contents of the counters 39 and 40. The AND element 34 serves to set the counters to the zero state after the addresses in the counters 39 and coincide. 40. The OR element 42 serves to form the resolution potential for the AND 31 element, through which the clock pulses from the generator 43. This potential is generated when at least one write or read request is received. The delay elements 44-46 are designed to synchronize the operation of block 6. Pulse from the output of element I 32 interrogates the state of flip-flop 35. A pulse from the output of delay element 44 polls the state of flip-flop 36. Pulse from the output of delay 45 will query block 3 memory for recording or reading information. The pulse from the output of the delay element 46 resets the flip-flops 35 and 37 or flip-flops 36 and 38 after performing read or write modes through the corresponding prepared elements 28 and 29, the same pulse resets the counters 40 and 39 of the black And 34 when matching read and write addresses.

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The control unit 4 is designed to control the data collection processes and output information from the device. Control unit 4 outputs to the system control line a periodic sequence of address codes of information output blocks 1 and address codes of information input blocks 2, as well as block markers 2. In control block 4, pulse generator 58 serves to generate a pulse train whose tracking frequency determines performance systems in general. The counter 56 is designed to form the addresses of the memory node 55 by counting the pulses of the generator 58. The memory node 55 is designed to store and store the original data to organize the collection of information from the blocks 2 and output it through the corresponding blocks 1. The register 54 serves to store and store on time period of the frequency generator 58 of the contents of the node address 55. The register 54 contains the address of block 2, the address of block 1, the marker of block 2 and the system marker. The system marker is the service signal of the control unit 4, according to which the counter 26 is set to the zero state, a generator / org 58 is delayed on the delay element 53. The counter 56 is reset to the zero state via the element 57. The pulse from the output the delay element 53 is used as a read request signal and is output to the output 51 of the control unit 4. The delay element 52 is designed to form a gate for blocks 1.

Information output blocks 1 are designed to receive information from blocks 2 and output it through blocks

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1 to the information receiver; In blocks 1, the levels of electrical signals are electrically matched to the levels of information receivers. Comparison element 60 and element 61 form a block code selector for selecting the corresponding block 1 when outputting information. At one of the inputs of the comparison element 60, the code number of this block is set, and the other input receives the current code of the block number 1 via the control bus of the system (input 50). If the codes match, the prepared information I 61 from the input 66 is written into register 63. Within 10

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Writing information to register 63 is carried out on the leading edge of the strobe arriving at input 59. Delay element 65 serves for a small strobe delay, which builds information on elements And 62, Shapers 64 are designed to electrically match the signals of unit 1 and receiver .

The information input units 2 are intended for receiving, switching, and converting into a digital parallel binary, analog, analog-discrete and discrete J5 electrical signals by a signal from sensors or matching and normalizing devices. Each block 2 is assigned an address - sequence number by setting the corresponding code on the code selector. In block 2, using the code selector, only those current addresses are sampled, the code of which corresponds to the number set in this block 2.

Figure 7 shows an example of building one of blocks 2 that performs frequency conversion — a code over several independent channels. Timer 72 in block 2 is used to set the time interval during which the frequency is converted to a code. Counters 71 are designed to count pulses of measured frequencies for each channel of block 2, which are fed to the counting input of counters from input 8. Static registers 75 store the codes of converted frequencies on several channels. The pulses of the timer 72 overwrite the contents of the counters 71 into registers 75. These same pulses, via the delay element 73, reset the counters to the zero state. Thus, the input frequency pulses are counted for a certain period of time generated by timer 72. Multiplexer 76 is designed to output the contents of registers 75 to output of block 2. The operation of multiplexer 76 is controlled by counter 78. The code selector of block 2 includes comparison element 77 and two elements And 79 and 80. If the code of the block number 2 coincides with the current code on the control highway, the comparison element generates a signal permitting the operation of multiplexer 76 and. element 79. Pulses from input 51

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through the element 79 and the delay element 74, the unit is added to the counter 78, the code of which controls the operation of the multiplexer 76, which connects the corresponding register 75 to the output of block 2. The counter 78 clears through the element 80 when the frame marker of the given block arrives.

The device works as follows.

The information input units 2 commute and transform the input signals, each according to their own algorithm. The result of converting the input signals is a parallel binary code outputted by blocks 2 to the device data highway. The information content of block 2 is determined by the number of information words per second that are output by this block upon the request of control block 4, which generates address addresses to block 2. Each block 2 is assigned its address — a sequence number which is decoded by the code selector. Thus, in each block 2, only those addresses are sampled, the code of which matches the number set in the corresponding block 2. The priority block for the formation of the address is included in the device on the rights of block 2, which has its own number and code selector.

The table shows an example of building a system frame.

2 1 1 3 2 2 2 2 2 1 1 3 2 2 2

1 4 2 3 5 5 5 5 1 4 2 3 5 5 5

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Table continuation

The operation of the device is determined by the system frame loaded into unit 55 of block 4.

Each control word of node 55 contains the block address code 1, the block 2 address code, the block 2 marker bit, and the system marker bit. The words of node 55 are periodically output to the device control bus and are accompanied by two pulses — the first is intended for block 2 and is a read request for information, the second is used in blocks 1 as an information strobe, the code of block 1 address 1 goes to all blocks 1 and indicates the direction issuing information. The address code provides for parallelization of the information flow over several outputs. The code address of a block is perceived by a block whose code matches the address code on the control bus. The address code of block 2 enters all blocks 2, including block 6. The frequency of issuing words by node 55 is determined by the selectable frequency of the generator 58 of pulses of block 4. The pulse of the frequency of generator 58 adds 1 to counter 56 and produces a call to node 55. This same pulse, the delayed element 53 delays the time required for the operation of the node 55 to write the control word to the register 54. The same pulse arrives at output 51 as a read request pulse of the corresponding blocks 2 and block 6. The generator pulse 58 delayed by the delay element 52 delays blunt to the output 59 of block 4 and further to the inputs of all blocks 1 as an information strobe. If a system marker is present in the control word, then the pulse from the output of the delay element 53 through the And 57 element sets the counter 56 to zero

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A new state, and the cycle of operation of the device is repeated.

I At the input 8 of the data selection block 5, data are received in the form of a phase-shift keyed code. Each data file represents one command and a certain number of information words. Unit 5 of data selection selects only those information arrays that are specified. Thus, the system is not overloaded with extraneous information. The decoder 9 provides decoding of the received arrays | And yields at the output the signs of command and information words, a serial binary data code, a signal. Data sprinkling and synchronization pulses. The decoder 9 is implemented on a 588VGZ chip. When a command word is received from the decoder 9, the trigger 21 is set to 1 by the one-shot 16 signal, and the trigger 18 is set to O. The command word is formed in the shift register 14. After receiving the command word in the register 14, part of it contains is decoded by the decoder 20. In this case, if the corresponding output of the decoder 20 is allowed by setting a single potential on the switch 19, then the input D of the flip-flop 18 will also have a single potential, and the signal of the one-shot 15 through the element 22 delays and element 12 translates trigger 18 into one state, and the pulse from the output of delay element 23 through element 11 enters output 25 of the block and then into block 6 as a request signal for writing this command word. Following the command word, the entire array of information words belonging to the given command word will pass. In this case, the trigger 21 will be set to the zero state on the first sign of the information word by the signal from the one-shot 17, therefore the element 12 will be blocked and the trigger 18 will remain in the same condition until the next control word. All command and information words are stored in buffer register 13 after they are formed in register 14. If the command word is not enabled on switch 19, then trigger 18 will not be set to one and the entire information array belonging to this

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Mandnu word will be blocked. The output information is fed to the output 24 of the block from the buffer register 13 and the trigger 21. The timing diagram of the operation of block 5 is shown in Fig.8. From block 5, the information enters memory block 3. Combining the processes of recording and reading information in block 3 is provided by block 6. Since there is a significant difference in the speed of receiving information in block 5 and its output to the device, block 6 ensures that the process of writing and reading data in block 3 is combined by organizing information buffering in floating memory, provides maximum system performance.

Suppose that in block 3 there is information that is to be issued and at the same time in block 6 there are two requests: Read request and Write request. Requests are stored on the respective triggers 35 and 36. The unit potentials of these triggers through the OR element 42 allow the operation of the element 31, through which the generator 43 pulses begin to pass, the delay elements 44-46 form the time diagram of the block operation shown in Fig.9. The pulse from the output of the element And 31 overwrites the read request from the trigger 35 to the trigger 37 and adds 1 to the counter 40. In this case, the write request to the trigger 38 will not be overwritten, since the pulse from the output of the delay element 44 will be blocked on the element And 33 by potential trigger units 37. Thus, block 6 will first read the data from block 3. The potential from the output of trigger 37 determines the type of operation of block 3, and also controls the operation of multiplexer 41, through which the address from counter 40 is output to block 3 . The pulse from the output of the delay element 45 arrives at the output 49 as a pulse of appeal to the block 3.

Upon completion of the read cycle, the pulse from the output of delay element 46 through preparatory element AND 28 resets the triggers 35 and 37 to zero. Since the trigger 36 remains in the single state, the element And 31 continues to remain open, and the next generator pulse will pass

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to the output element And 31. At the same time, the write request signal stored on trigger 36 will be overwritten into trigger 38 by a pulse from the output of delay element 44 through open element 33. At the same time, one will be added to counter 39. The multiplexer 41 is set to the zero potential of the trigger 37 in the mode of issuing the address of the record from the counter 39. After the output signal is addressed to the side 3 from the output of the delay unit 45, the triggers 36 and 38 through the open element 29 are set to the zero state. At the same time, And 31 is closed until the next write or read requests. When the contents of counter 39 become equal to the contents of counter 40 after the next maintenance of the read request, i.e. when the last address of block 3 is read, by which information is recorded

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Matsi, the comparison element 27 will prepare for operation the E 34 element, and the pulse from the output of the delay element 46 will set the counters 40 and 39 to zero. In addition, the potential of the comparison element 27 will close the AND 30 element, which will result in blocking requests for reading information. The read request will be resumed when block 3 begins to receive new information and the contents of counter 39 will become an excellent zero. To work with block 6, the formation of the marker of block 2 in block 4 is not required, since the information has its own command words containing the characteristics of the data arrays.

Claims (4)

1. A device for exchanging data between a source and a receiver of information, comprising a first information output unit, a memory unit, a group of information input units, and the information inputs of the information input units form a group of device inputs for connection to the information outputs of information sources, the information output of the first unit the information output is the output of the device for connection to the information input of the first information receiver, while the information output of the memory unit is connected to the information information outputs of the group of information input units and with the information input of the first information output unit, characterized in that improving performance by providing hardware distribution of output information streams, a priority address generation block, data selection block, M-1 information output blocks and control block are entered into the device, the information input of the data selection block being a device input for connecting information sources to the command outputs , information outputs M-1 of information output units form a group of device outputs for connecting information receivers to information inputs M-1, while The strobe output of the control unit is connected to the gate inputs M of the information output blocks, the address inputs of which are connected to the address inputs of the group information input block, the address input of the priority address generation unit and the address outputs of the control block, the second gate output of which is connected to the gate inputs blocks for entering information of the group and with the input of the request for reading the priority block for generating the address, the input of the write request of which is connected to the outputs of the record of the data selection block, info the output of which is connected to the information input of the memory unit, the write-read input, the synchronous input, the address input and the information output of which are connected respectively to the write-read output, with the synchronous outputs, to the address output of the priority address generation unit and to the information inputs of the M-1 blocks output information. 2. The device according to claim 1, characterized in that the control unit comprises a pulse generator, an address counter, a memory node, a control code register, an And element, two delay elements, the output of the first delay element being the first gate output of the block, the second output the delay element is connected to the first input of the element I, to the input of the first delay element, to the synchronous input of the control code register, and is the second gate output of the block, the first information output of the control code register is the address output of the block, in that the pulse generator output control unit is connected to the input of the second delay element with synchronous input 0 five 0 five of the memory node and with the counting input of the address counter, whose information inputs are connected to the information inputs of the control code register, the second information output of which is connected to the second input of the And element, the output of which is connected to the installation input of the address counter, the output of which is connected to the address input of the memory node . 3. The device according to claim 1, characterized in that the priority address generation unit contains two comparison elements, four triggers, two counters, a multiplexer, seven AND elements, an OR element, three delay elements, a pulse generator, the first and second inputs the first comparison element is the address input and the block address setting input, the first input of the first element is the input of the read request for the block, the single input of the first trigger is the input of the write request for the block, the information output of the multiplexer is the address output of the block, the output of the second trigger is connected with the control input of the multiplexer, with the first inputs of the second and third elements And are the write-read output of the block, the output of the first delay element is connected to the input of the second element and $ is the sync output of the block, while the output of the pulse generator is connected to the first input of the fourth AND element, the second input of which is connected to the output of the OR element, whose input is connected to the output of the third trigger and to the first input of the fifth element And, the second input of which is connected to the output of the fourth element And and the input of the third element delay, the output of which is connected to the input of the first delay element and to the second input of the third element K, the third input of which is connected to the second input of the OR element and to the output the first trigger, the zero input of which is connected to the output of the sixth element And with the zero input of the fourth trigger, the output of which is connected to the first input of the sixth element And, the second input of which is connected to the second input of the second element And, to the output of the second delay element and to the first input of the seventh element And, the second input of which is connected to the output of the second comparison element and to the second input of the first element And, the third input and output of which are connected respectively to the output the first element of the comparison and with the single input of the third trigger, the zero input of which is connected to the output of the second element And with the zero input of the second trigger, the single input of which is connected to the output of the fifth element And and the counting input of the first counter, the output of which is connected to the first information inputs of the multiplexer and the second comparison element, the second information inputs of which are connected to the output of the second counter, the counting input of which is connected to the output of the third And element and the single inputs of the fourth trigger connected to the output of the seventh element I. 4. The device according to p. Differs in that the data selection block contains a decoder, a shift register, two triggers, a buffer register, a decoder, a switch, three AND elements, two delay elements, three one-vibrators, the information input, the decoder being the information input of the block , the information output of the buffer register and the output of the first trigger, connected to the first input of the first element I, form the information input of the block, the output of the second element I is the output of the block write request, controlling its inputs five 0 five 0 five the switch form the inputs of the block code setting, while in the data selection block the decoder information output is connected to the information input of the shift register, the synchronization input of which is connected to the output of the third element And, the fourth input of which is connected to the first synchronous output of the decoder, the second synchronization output of which is connected to the second input of the third element Both with the start input of the first one-one vibration, the output of which is connected to the input of the buffer register and the input of the first delay element, the output of which is connected to the input the second delay element and the second input of the first element, whose output is connected to the synchronous input of the second trigger, the zero input of which is connected to the single input of the first trigger and to the output of the second one-oscillator, the start input of which is connected to the third synchronous input of the decoder, the fourth synchronized output of which is connected to the start of the third single-vibrator, the output of which is connected to the zero input of the first trigger, the output of the second delay element is connected to the first input of the second element And, the second input of which is connected with the output of the second trigger, the information input of which is connected to the output of the switch, the information inputs of which are connected to the outputs of the decoder, the information inputs of which and the buffer register are connected to the information outputs of the shift register. ts & U7 C8 -jrn aopfca 0 " tfaMcttffaffe with / r0yo w out ten J-Lnn-TUi-n-n-n-ri-n Vsh. 13 8th / 4 F77 S & /%. 21 A / f / 6 tx-16,25 # ff $ faex06 # 0 # is a shit F i Fa 8