SU1675890A1 - Test sequencer - Google Patents

Abstract

The invention relates to computing, to devices for generating tests. The predominant use area is the creation of test equipment for digital devices. A feature of the device is that it allows repeatedly - by M + 1 times - increasing the number of generated test signals, which is of paramount importance for creating automated diagnostic systems for digital devices. The aim of the invention is the expansion of technical capabilities due to the multiple increase in simultaneously formed various independent from each other sequences of digital signals. The goal is achieved by the introduction of additional memory blocks 6, a demultiplexer 7, a group of 8 modulo two elements, registers 9. 5 Il.

Description

2,

The invention relates to computing, to devices for generating tests, mainly to creating test equipment for digital devices.

The aim of the invention is the expansion of technical capabilities due to the multiple increase in simultaneously formed various independent from each other sequences of digital signals.

FIG. 1 and 2 shows the structural scheme of the proposed device; in fig. 3-5-time diagrams of the device.

The device contains a clock generator 1, a counter 2, a switch 3, a comparison block 4, a non-AND element 5, memory blocks 6, a demultiplexer 7, modulo-two elements 8, registers 9, an inverse output 10 of the clock generator, outputs 11 elements of 8 modulo two, a group of 12 inputs of the sequence number, a group of 13 inputs of the start of a sequence, an input 14 of start, a group of 15 inputs of the end of a sequence, an input 16 of operation enable, an input 17 of the recording resolution, a group of 18 inputs of specifying the sequence view, a group of 19 outputs and a group of 20 inputs you bora group outlets.

The device works as follows.

The operation of the device begins with its programming for the subsequent generation of digital signals of the required form. Programming is accomplished by alternately recording information in the blocks 6 of the information generated by the digital signals.

Let us consider an example of recording information about one of the sequences of digital signals into one of the memory blocks 6, reflecting the changes in time of each of the digital signals generated by the corresponding output (discharge) of the device, and then generating a sequence of digital signals from it in accordance with the time diagram, shown in fig.Z. The discretization of the changes in time of the digital signals depicted in FIG. 3 is equal to the period T of the clock pulses generated by the clock generator 1. The state of the digital signals

output signals of 0.1 bits (K-1)

the memory block during any time interval indicated in FIG. 3 is expressed by a binary number, in which its zero discharge corresponds to the state of the digital signal at the output of the zero discharge of the memory block; the first discharge corresponds to the state of the digital signal at the output of the first discharge Yes, the memory block (K-1) -th bit-state of the digital signal at the output (K-1) -th bit of the memory block. In this case, the number 1 ... 1100, corresponding to the state of digital signals during the time interval 0 - to, is recorded in the memory cell with the address A, the number 1 ... 1001, corresponding to the state of digital signals during the time interval t0 - ti , - to memory cell with

address AI and, finally, the number 1 ... 0110.

corresponding to the state of the digital signals during the time intervals tp-2 - tp-i, is recorded in a memory cell with the address Ap-1.

Consider the procedure for recording information in one of the blocks of 6 memory. Before recording, at the inputs of the device are installed: at the input 14 of the start (Figures 1 and 2) - a logical unit, at the input 16 of the work enable - a logical zero, at the input 17 of the recording resolution (i.e., at the inputs of the WR memory blocks 6) - logical unit, on the group of 20 inputs (i.e., on the group of address inputs of the demultiplexer) - the binary address selected for recording one of the M blocks of 6 memory. At the same time, at the output of one of the M logic elements 8 of the modulo two, an enable signal E of a logical zero is generated for one of the M + 1 memory blocks 6.

The switch 3 (FIG. 2) passes to the address input groups of the memory blocks 6 the address set on the group 12 of the sequence number inputs (FIG. 1). When recording information into the indicated cells of memory block 6, it is necessary, in accordance with the timing diagram (Fig. 4), to set the address of the memory cell on the group of 12 inputs, and the corresponding values of the bits of the binary number reflecting the state on the group of 18 inputs of specifying the type of device sequences. digital signals, and then at input 17 of the recording resolution, a logical zero. Before installation, the address of the next memory location at input 17 of the recording resolution is set to a logical unit on the group of inputs 12. Thus, in the area of the memory block 6, beginning with the address of the AO and ending with the address Ap-1, information about the sequence of digital signals shown in FIG. 3 is stored and stored. If necessary, information on other sequences of digital signals can be recorded in other areas of the storage unit b (with different values of A and Ap-i). The remaining memory blocks 6 are programmed in the same way, and the corresponding binary selection address of the next memory block 6 is set on the input groups 20 (Figures 1 and 2).

After programming is complete, the device is prepared to form one of the sequences of digital signals recorded in blocks 6 of the memory. At the same time, a logical unit is installed at the input 17 of the recording resolution, the starting address of the memory area storing the information about the selected for forming a sequence of digital signals (in this case) is set at the group 13 of the inputs of the beginning of the sequence (i.e., the group of information inputs of the counter 2). In the example, this is A0, which has the same value for all memory blocks 6), and the final address of this memory region (in this clause Imera is Ap-i). The logic unit previously installed at the start 14 of the input goes through the NE-5 logical element to the input 11 of the record 2 counter recording and puts it into parallel loading mode, in which the clock pulses F from the direct output of the master oscillator 1 are received at its C input. the front is recorded in counter 2 from its group of information. the start address A0, which is set on the output group of counter 2. The formation of a sequence of digital signals is carried out in accordance with the time diagram (figure 5), where, for greater clarity, the time delays during the formation and propagation of signals are not shown, and the settings input 16 allows the logical unit to work (at time 0 on the diagram). At the same time, at the outputs 11 of the group of 8 addition elements according to module Two, the levels of logical zero are set, which, arriving at the inputs CS of memory blocks 6, allow reading of information from all memory blocks 6. The formation of the selected sequence of digital signals is carried out as a result of sequential reading of information from the cells of memory blocks 6, starting with cells with address A0 and ending with memory cells with address Ar-h. Switch 3 transmits address address A0 from address output groups A of memory block 6 from output group 2 of counter 2. At time 0, information AO 1100 that can be read from the AO memory cell appears in the output group of block 6 signals in the time interval 0 - to (fig.Z). Then, at time point 0 - + T / 2, the positive edge of the clock pulse F. arriving at the C input memory of memory block 6 from the inverse

the output of the master oscillator 1. is recorded in register 9 information 1 ... 1100, which appears on its group of outputs. Relevant information also appears on the DO output groups of the remaining 6 units of the 5th unit. Simultaneously, the logical zero from the device start input 14 is also fed to the input of the element NE-5, to the second input of which from the equality output

0 of the comparison unit 4 also receives a logical zero, corresponding to the absence of a coincidence signal.

Thus, from the output of the logic element 5, to the input of the recording resolution

5 counter 2 at time 0 + T / 2 enters the logical unit and translates it into account mode. Further, under the influence of the clock pulses entering the clock input at times to, titp-2 on

0, the output group of the counter 23 alternately forms the addresses AI,

A2Ar-1 memory cells that are received

through switch 3 to groups of address inputs of memory blocks 6, and to group of outputs

5 which alternately read information 1 ... 1001 appears in the time interval to - ti 1 ... 0110 - in the time interval

time tr-2 - tp-i, which is under the influence of arriving at the synchronous input register 9

0 with a delay of T / 2 appears at the outputs of register 9. Similarly, information from the remaining blocks of 6 memory is read in the same way.

. Thus, from the information read from blocks 6 of the memory at the outputs 19

5 of the device, the generated sequence of digital signals is folded according to the timing diagram of FIG. After the counter 2 forms the address Ap-1, which coincides with the final address set on the group of 15 inputs, a logical unit appears at the output of the equality of the comparison block 4, corresponding to the generation of a logical matching signal, translating counter 2 through

5, the element 5 is in parallel loading mode, in which, under the influence of the next clock pulse F, arriving at the time point tp-i at the counting input of counter 2, its group of outputs is set

0, the start address is A0, where the logical output of the comparison unit 4 is a logical match signal (i.e., a logical zero appears) and the counter 2 is again converted to the counting mode, the second generation of the specified sequence of digital signals begins, etc. . To stop the formation of this sequence of digital signals, it is necessary to set a logical unit at input 14 of the device start, which will transfer counter 2 through element 5 from the counting mode to parallel loading mode (initial setting).

To form another sequence of digital signals (information about which was previously recorded in memory blocks 6 when programming a device), a logical unit is set at input 14 of the device launch; on group 13 of inputs, the starting address of the memory area storing information about another digital signal sequence , on a group of 15 inputs, an end address of a memory area storing information about a different sequence of digital signals, and then a logical zero is again set at start input 14. Further, the formation of another sequence of digital signals is similar.

Claims (1)

Claims An apparatus for generating test sequences comprising a clock generator, a counter, a switch, a comparison unit, a NOT-AND element and a first memory block, the direct output of the clock generator connected to the counter input of the counter, the group of discharge outputs of which is connected to the first group information inputs of the comparison unit and with the first group of information inputs of the switch, the second group of information inputs of which is the group of inputs of the device sequence number, the information group tional input counter is a group of input devices start sequence counter write enable input connected to the output element and the first inverted input of which is input to start the device, a second inverted input connected to an AND the equality output of the comparison unit, the second group of information inputs of which is the input group of the end of the device sequence, the control input of the switch is the input for enabling the operation of the device, characterized in that, with the aim of extending the functionality by repeatedly increasing formed by different and independent of each other sequences of digital signals, m - 1 memory blocks are entered into the device, where m is the number of output groups of the device, a demultiplexer, a group of adding elements modulo two and m registers, with the enable inputs of recording registers connected to the inverse output a clock generator, a group of address inputs of the memory blocks are connected to a group of outputs of the switch, the write enable inputs of the memory blocks are connected to the write enable input of the device, the groups of information inputs of the blocks pa tee connected to a group of entries specifying the type device sequences, the information input of the demultiplexer is connected to the first inputs of the elements of addition modulo two and to the control input of the switch, the inverse inputs of the demultiplexer connected to the second inputs of the add-on elements modulo two groups, the outputs of which are connected respectively to the read-out inputs of the memory blocks, the group of memory blocks from the first to the tth one 5 are connected respectively to the information inputs of the registers from the first to the th, the groups of outputs of the registers are groups of outputs of the device, the group of address inputs of the demultiplexer is a group 0 device selection inputs. l Г1 / / то .-I 1-iIit handles Q pshvnvi he   pshvnoiv  L J ° O I .owoggdcoft    m og-iQomy 1 G1 / / that 1-iIit pshayoi org oqisaevd og-i-y dkhpd I I i i l pshvnnyi VU -ovn adkaeoa udoh / chd - | | I I ., drank G I G -ovgadmem -4 IIt og-edoh / chd t, a, l nuiKHDU wu i H-ok Dg "/ f orf. I / og-2 wooden handles Q pshvnvi he   pshvnoiv j L J ° O I .owoggdcoft 0  / V g-oj  / rf i1 g pshioi op ° V- ° K og gcxwp oifwatfj jatfei 0689191 H ozgb about i L h w ft A  GC Gygy f ewoi ri with A // Ј% iDG XZ DCIIZZf //  „LJ LJ FIG. 4  fi i   rtz / Y / f (  ft 01  .twp ± /; ) c :: oDe fimv / "w / w 7l -Л-Л- - / -Ј -ЛfwfO & tffЈ f ...... 11/1 / гdgzhL11 faff / ret rtffrttffts  ; Ln j i rr :: L rL foxyi /} f..y., 1 / y / ) C.jЈ : cn frojff o Fig 5 Fig 5