SU1695316A1 - Device for information exchange - Google Patents

Abstract

The invention relates to computing and can be used in control computer information exchange systems with objects over a serial channel by groups of p-bit words. The purpose of the invention is to expand the field of application due to the possibility of exchanging groups of p-bit words over a serial channel. The device for information exchange contains a trigger, a pulse generator, an AND element, an NAND element, a pulse shaper, an OR element, tact counters, a register, a delay element, a permanent memory block, a bus driver, a control register, two signal switches, a write counter reading, two items are NOT. memory block, word counter. 5 ill., 1 tab.

Description

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The invention relates to computing and can be used in control computer information exchange systems with objects over a serial channel by groups of p-bit words.

The aim of the invention is to expand the field of application due to the possibility of exchanging groups of p-bit words over a serial channel.

Figure 1 shows the functional diagram of the device for the exchange of information; FIGS. 2-5 are timing diagrams of operation in the Record, Transmit, Receive and Read modes, respectively.

The device contains (Fig. 1) trigger 1, a pulse generator 2, an AND 3 element, an AND-4 element, a pulse shaper 5, an OR 6 element, a clock cycle counter 7, a register 8. a delay element 9, a permanent memory unit 10, bus driver 11, register

12 controls, first signal switch 13, write-read counter 14, NOT elements 15 and 16, second signal switch 17, main memory unit 18, word counter 19, parallel information inputs 20 and device outputs 21, device start input 22, input 23 reset the device, the first synchronization input 24 of the device, the device 25 read input, the device operation mode input 26, the serial information input 27 and the device output 28, the input 29 of the code for the number of transmitted-received p-bit words on the serial channel, Torah synchronization input 30, output 31 reception clock and the transmission-output device 32 starting pulse.

The permanent memory unit 10 may be implemented, for example, on two chips of the type 556 PT5, programmed in accordance with ON SL

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with table. The cycloprograms of the Record, Transmit, Receive and Read modes, located in the four banks of memory, allow the exchange of groups of 16-bit words.

The device works as follows.

The exchange of information between computers and objects over a serial channel is carried out under the control of a computer that generates the Reset, Start, Read signals, K code, OA and A1 signals, specifying the operation mode, C and C clock pulses.

A full cycle of information exchange includes the sequential operation of the device in the Record, Transmit, Receive and Read modes. At the request of the user, any options for one-way exchange.

The principle of operation and the device control algorithm are considered on the example of organizing a full cycle of exchange with the transmission of three 16-bit words over a serial channel.

In the Record mode, an array of three 16-bit words is formed in the RAM block 18. The array formation algorithm is as follows:

1. Installation of signals A0 0; A1 0 at the inlet 26,

2. Formation of the H-signal Reset at the input 23.

3. Installation on inputs 20 of the first transmitted word.

4. Formation of the H-pulse C at the input 24.

5. Formation of the L-signal. Start at the input 22.

6. Analysis of the state of the trigger 1. When Q 0 the continuation of the algorithm.

7. Installation on inputs 20 of the second transmitted word.

8. Formation of a C pulse at the input 24.

9. Forming the start-up signal 22.

10. Analysis of the state of the trigger 1. When Q; 0 continuation of the algorithm.

11. Installation on inputs 20 of the third transmitted word,

12. Formation of a C pulse at the input 24.

13. Signal shaping Start at input 22.

When forming a signal, a single pulse at input 23 is reset — counter 14 is reset to zero. On the leading edge of the C pulse at input 24, the 16-bit word from inputs 20 is written to register 8. The recorded word can

be controlled by software when generating a read signal at input 25, which ensures the transfer to output 21 of the contents of register 8 via bus driver 11 to the control computer data bus. The Start signal at input 22. is set to one state trigger 1. At the same time, the Start signal is inverted by the element.

0 AND-NOT 4, is fed to the input of the imaging unit 5 pulse. On the leading edge, the pulse former 5 generates a short pulse arriving at the reset inputs of the counter 7 and the control register 12. The control switch 12 and counter 7 are reset to the zero state. The unit level from the output of the trigger 1 is fed to the first input of the element 3, allowing the passage of pulses from the generator 2 pulses to the summing input of the counter 7 and through the delay element 9 to the synchronization input of the control register 12. Signals AO 0; A1 0, the first bank of the permanent memory unit 10 is selected, in which the Recording mode sequence diagram is located (Fig. 2). Signal log. About with the inverse trigger output 1 register 8 is transferred to the shift mode. On the leading edge of each pulse generator 2 (sequence F)

0, the counter 7 changes its state upwards. The contents of the counter 7 are addressed to the cells of the fixed memory unit 10, the contents of each addressable cell of the fixed unit 10 are rewritten with a delay in the control register 12. The presence of register 12 in the device is necessary to eliminate the states at the outputs of the block 10 of the permanent memory when modifying the addresses. Availability

0 elements 15 and 16 provide an unselected state of the RAM 18 at the initial moment of formation of the cyclogram when the control register 12 is reset and eliminates unauthorized access to block 18. The zero signals on the second and seventh outputs of the register 12 provide the information transfer by the switches 13 and 17 from the first entrances to the exits. After the fifth pulse of the sequence F

0 a zero signal is selected at the sixth output of the register 12 by a RAM block 18, to the information input of which through the switch 13 a signal comes from the output of the high register bit 8. After

5 of the sixth pulse of the sequence F (Fig. 2), the named signal at the zero signal at the fifth output of the register 12 is recorded at the zero address in the operational memory block 18. After the eighth pulse F, the state of counter 14 is modified and the contents of the register 8 are shifted by one bit to the high bits by register AST and C, respectively. Pulse C from the first output of register 12 of control is fed to the synchronization input of register 8 through the element OR 6. Next, the described procedure is repeated, and the contents of register 8 are sequentially copied to memory module 18 at the first 16 addresses of the first memory bank 18 (figure 2, 0).

At the end of the write cycle, at the eighth output of register 12, a reset pulse is generated, which enters the reset input of trigger 1 via switch 17. Trigger 1 is reset to the zero state, thereby interrupting the sequence of pulses F and signaling the readiness of the device to restart. At the same time the reset pulse through the element AND-NOT 4 is fed to the input of the imaging unit 5 pulse. The latter generates a short pulse that resets the counter 7 and the control register 12 to the zero state, preparing the device for restarting. Signal O. from the inverse trigger output 1, the register 8 is switched to the parallel code recording mode. After writing in parallel format to register 8 of the second transmitted word, the device is restarted (input signal 22).

After the start signal, the second transmitted word is recorded at the next 16 addresses of the RAM block 18.

In a similar way, a third word is recorded in memory unit 18.

Thus, in the Record mode, in the memory block 18, an information array is formed, which is a group of three 16-bit words.

Transfer Mode. A serial channel is transmitted (output 28) of a group of three words previously recorded in block 18. The mode implementation algorithm is presented as follows:

1. Formation of the H-signal Reset at the input 23.

2. Installation of signals AO 1; A1 0.

3. Installation at the inputs 29 of the K 3 code. 4. Formation of the H-pulse C at the input 30.

5. Signal formation Start at input 22.

Signals AO 1; A1 0 selects the second bank of the permanent memory unit 10 in which the Transmit mode sequence is placed (Fig. 3). The single signal at the second output of the register 12 permits the transfer from the entrance of the switch 17 to the output, and at the fifth output provides the read mode of the operational memory block 18. Each read bit is accompanied by a receive-transmit sync Cp (ninth output of register 12), each successively transmitted word is preceded by a starting pulse (the tenth output of register 12). When transmitting three words, the sequence diagram (Fig. 3) repeats three times until the word counter 19 is reset, to the subtracting input of which impulses come from the eighth output of register 12. This impulse goes through the switch 17 to the reset input of trigger 1, zeroes the last one, which signals about the end of the transfer of three words.

Receive Mode In the specified mode, a group of words is received over a serial channel (input 27) and placed in the second bank of the RAM 18.

The algorithm for implementing the mode is as follows:

1. Signal shaping Reset at input 23.

2. Installation of signals A0 0; A1 1.

3. Installation on inputs 29 of K 2 code.

4. Signal shaping Start at input 22.

Signals AO 0; A1 1 selects the third bank of the permanent memory unit 10, in which the receive mode cyclogram is located (Fig. 4). Single signals at the second and seventh outputs of the register 12 allow the transfer of information from the second inputs of the switches 13 and 17 to their outputs. Signal B 1 (the fourth output of register 12) selected the second bank of the random access memory block 18.

After the device is started, a starting pulse is generated preceding each received word. In response to each receive-transmit Cx clock, the source of information sets a 27-bit input, recorded at the time of the zero state of the fifth register output 12 at the corresponding address in the second bank of the operational memory block 18. To receive two words, the sequence diagram (Figure 4) is repeated twice until the word counter 19 is zeroed. At the moment of resetting the counter 19, the trigger 1 is reset, signaling the end of the Receive mode and the interruption of the sequence of pulses F.

Reading mode. The array of received information is read from the second bank of the RAM 18 with 16-bit words. The Read mode algorithm is presented in the following form.

1. Installation of signals AO 1; A1 1.

2. Signal shaping Reset at input 23.

3. Signal shaping Start at input 22.

4. Analysis of the state of the trigger 1. When Q 0, the algorithm continues.

5. Signal shaping Read at exit 25 to read the first word.

6. Signal shaping Start at input 22.

7. Analysis of the state of the trigger 1. When Q 0, the algorithm continues.

8. Formation of L-signal Read input 25 for reading the second word.

Signals AO 1; A1 1 the fourth bank of the permanent memory unit 10 is selected, in which the read mode sequence diagram is placed (Fig. 5). The zero state of the seventh and one state of the fifth outputs of the register 12 cause the switch 13 to transmit information from the first input to the output and provide the reading mode of the block 18. Each bit from the output of the block 18 along the leading edge of the pulse C shifts to the register 8. The pulse AST modifies the state of the counter 14. At the end of the cyclogram, the trigger 1 is zeroed, the pulse sequence F is interrupted. In register 8, the first received word is sequentially rewritten from the second bank (B 1) of block 18. During the formation of the read signal, the bus driver 11 is selected and the first read word is transmitted to the data bus of the control computer. By restarting from the memory block 18, the second word is sequentially rewritten into the register 8 and transmitted to the control computer data bus in a similar manner.

Claims (1)

The invention includes a device for exchanging information, a trigger, a pulse shaper, an OR element, a write-read counter and a register, the synchronization input of which is connected to the output of the OR element, and the mode control input with an inverse trigger output, characterized in that expanding the field of application by providing t the possibility of exchanging groups of p-bit words over a serial channel, a pulse generator, an AND element, an NAND element, a clock counter, a delay element, a fixed memory block are entered into it and, bus driver, control register, two signal switches, two NOT elements, a RAM block and a word counter, the output of the pulse generator connected to the first input of the AND element, the second input of which is connected to the forward output of the trigger, and the output to the summing to the input of the clock counter and through the delay element to the register synchronization input control group whose information inputs are connected to a group of outputs of a permanent memory block, a group of address inputs of which is connected to a group of outputs of a clock counter, the reset input of which is combined with the reset input of the control register and connected via an impulse generator to the output of the NAND element, - the fourth outputs of the control register are connected respectively to 5 with the first input of the OR element, with the control input of the first signal switch, with the summing input of the write-read counter and with the upper address input of the RAM, fifth to eighth outputs The control register 0 is connected respectively via the first element NOT to the read-write input: the RAM block, via the second element NOT to the sample input of the RAM block, to the control input 5 of the second signal switch, to the subtracting input of the word counter, to the first input of the element NAND and the first information input of the second signal switch, the second information input 0 which is connected to the output of the word counter, and the output to the trigger reset input, the information input of the RAM block is connected to the output of the first signal switch, the first information input of which is connected to the output of the higher digit of the register, the output group of which is connected to the group of information inputs bus driver, the input of the record of the sequential code of the register is connected to the information output of the RAM block, the group of address inputs of which is connected to the group of outputs of the first counter, the input reset which is the device reset input, the setup 5, the trigger input is connected to the second input of the NAND element and is the device start input, the second input of the OR element and the input of the word counter record are the first and second inputs of the device’s synchronization, the two most significant bits of the address input of the permanent memory unit form the input of the device mode setting, the group of information inputs of the word counter is the group of inputs for specifying the number of exchange words, the group of outputs of the bus driver) and the group of information inputs of the register are respectively groups of inf rmatsionnyh device outputs and inputs, sample input bus shaper is input device readings, the second information input of the first signal switch and the output of the RAM block are the corresponding information inputs Record, I bank Transfer Mode, II Bank The device home and output, the ninth and tenth outputs of the control register are respectively the outputs of the receive and transmit clock pulses and the start pulse. Table continuation izziiniiEZLiiniziaiiiz.ii--. Start IT F -jimMmmK ... cs ty MMmEL ... with a five VI V2 AT Cnn R1 - Start (G F - Aldamshm m ::: U years mmmm ... with  «« IBBii MaBMM rt Vf i MMNNMMIWMWBHMMne iWBBBBBIia HMHHMHIV H HMMMH # " V2  " at  § «« «ННННММ ННМВМВ | M M «W 1N M W FIG. 3 H1 FIG. 2 n & fbf 2 3b5S789f6f 2/3 F - LSHSHLLLLSHP. CS W / R. ACm C, S vi Fv snITL mshmmmm ::: cs / L 6f 6263№656667686970 IS Phil A ttsh pa t 5 U