SU1383354A1 - Device for servicing requests - Google Patents

Abstract

The invention relates to computing and can be used in computing systems. The purpose of the invention is to increase speed. The device contains a register of 1 requests, groups of elements AND 2, 14, 16, buffer register 3 requests, elements OR 4, 18, 20, element NOT 5, trigger 6, delay element 7, element AND 8, block of elements AND 9, counter 10 the decoder 11, the group of elements OR 12, 13 and 17, the element OR NOT 15, the encoder 19. The device provides the implementation of a cyclic discipline of servicing requests with the formation of the binary code of the number of the source of the request, which can be used as the address of the service subroutine. 1 dw., 2 tab.

Description

from 00

with

with O1

four

The invention relates to computing and can be used in computing systems.

The aim of the invention is to improve the speed of the device.

The drawing shows a block diagram of the device.

The device contains the register of 1 requests, the group of elements AND 2, the buffer register of the requests, the element OR 4, the element NOT 5, the trigger 6, the element 7 delay, the element AND 3, the block of elements AND 9, the counter 10, the decoder 11, the group of elements OR 12 and 13, the group of elements AND 14, the element OR-NOT 15, the group of elements AND 16, the group of elements OR 17, the element OR 18, the encoder 19, the element OR 20, the interrogation 21 and the response 22 inputs, the ready output 23, the start input 24, signal output 25, address outputs 26.

The device works as follows.

In the initial state, the register 3, the trigger 6 and the counter 10 are set to the state “O (not shown)”.

The device provides the implementation of a cyclic discipline of servicing requests, with each successive cycle of selecting the source of the request beginning with polling the source, the number of which is one more than the number served in the previous cycle.

Requests from sources at inputs 21 are sent to the corresponding register bits 1, and since trigger 6 is in the "O" state, elements AND 2 are opened with a single signal from the zero output of the trigger 6. In this case, the recorded requests in register 1 are transmitted to register 3, which ensures tracking of incoming requests. In the presence of requests in register 1, an element OR is generated by a single signal, which arrives at the output 23 as a signal of the device. But the servicing device generates a trigger pulse at input 24, which is set to state 1 trigger 6, and in counter 10 a unit is added to its contents. When the device is initially turned on, the binary code of the unit is generated in the counter 10 in this case.

With the help of the elements OR 12 and 13, the operation of the elements AND 14 and 16 is performed, which provide for the cyclical mode of servicing requests.

The OR 12 elements are included with the outputs of the decoder 11 so that the AND 14 elements analyze the source requests, starting with the / th number, where i is the number of sources of the request, one greater than the source number served in the previous cycle.

The operation of the elements OR 12 is explained in Table. 1 and 2.

The elements OR 13 are included with the outputs of the decoder 11 so that the elements of AND 16 analyze the requests of the sources, starting with the first number in rst.

0

five

0

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OR 13 is as defined

Work items table. 3 and 4.

Using the OR-NOT 15 element blocks the selection of the request from the first to (s) if there are signals from the i-ro from the lth request sources.

The elements OR 17 and 18 provide the formation of a combined service request signal, and the binary code of the subscriber number that can be used as the address of the service program is generated by the encoder 19. In addition, the output signals of the encoder 19 are used to organize the selection of the next subscriber (source) in the following cycle operation of the device using the counter 10.

The operation of the device consider the following source data.

Nust in register 1 accept requests from 2, (n-1) and n-th sources.

Since the trigger 6 is in the zero state, these requests are transmitted to the register 3 to the corresponding bits through the open elements AND 2.

But input 24 receives a start signal, setting trigger 6 to the state "1, 5, and in the counter 10 a binary code" 1 is generated. The zero signal from the zero output of the trigger 6 blocks the reception in the register 3 of incoming requests to the register 1.

After some time, determined by the delay element 7 at the clock input of the decoder 11, a single signal is established.

At the first output of the decoder 11, a single signal is formed, which opens the first element And 14 and through the element OR 12 all subsequent elements And 14. In addition, the first input opens the element And 16i through the element OR 13i.

In this case, the discipline of the cyclic service is implemented in the following order of placing the numbers of the sources of queries: 1 2 - ... n-1 p.

Elements 14 are included with the outputs of register 3 in the priority scheme so that the priority of the source decreases with increasing number. Therefore, a single signal is formed at the output of the element I lg, and at the other outputs of the elements E 14 it is zero. A single signal, the converted element OR NOT 15 to zero, blocks the operation of elements AND 16.

thirty

40

45

50

At the output of the OR elements 17, the position code of the number two is formed, converted by the encoder 19 into the binary code of the number two, and at the output of the element OR 18, a request signal is received, which arrives at the computer. This signal is used to read the binary code from the outputs 25, and the corresponding input 22 generates a response signal. This signal is set to the state "On the second register bit 3, through the element OR 4 and the block of elements and 9.

opened by a single signal from the output of the NOT element 5, the binary code of the number 10 is received in the counter 10 and set to the state "About the trigger 6. After the trigger 6 is set to the zero state in register 3, they are in the state" 1 only (n-1 ) th and “th discharge. At the same time, the OR 20 element holds a single device readiness signal at the output 23. At the end of the service of the request from the second source, input 24 sends a start pulse setting trigger 6 to the state "1", and in the counter 10 the binary code of the number three is generated. In the future, the device operates as described above. In this case, the choice of the request for analysis from the third source is ensured, by virtue of which the discipline of the cyclic service is implemented in the following order of placing the numbers of the sources of the requests:

By a single signal from the third output of the descrambler 10 through the elements OR 122, ---, 12 ", the elements AND 14з, ..., And 14" are opened at the first inputs. Since register 3 records requests from (n-1) -th and n-th sources, a single signal is generated at the output of the AND 14p-2 element, through which the AND 16 elements are blocked by the OR-NOT 15 element. a position code is generated having one at the (rt-1) -th position. By means of the element OR 18, a request signal is generated, arriving at the output 15 of the device, and the binary code of the number (n-1) is set at the outputs 26.

Subsequently, the response signal is used to set the “O (n-1) -th bit of register 1 and trigger 6, as well as write a binary code (n-1) to counter 10, and the next order is set at the next start signal in the device accommodating source numbers for cyclic service: n - 1 - 2 - ..., n-1.

In accordance with this order and if there is a request in register 3 only from the n-th source, the binary number n is formed at the output 25. At this, the element OR 18 is opened from the output of the OR 17l element, and the block is closed through the HE 5 element elements AND 9. Therefore, the response signal for the n-th source through the element OR 4 is set to the state of "On trigger 6, the n-th register bit 1 and through the element And 8 counter 10. At the same time, a single signal at the output 23 of the device is removed.

If register 1 is in the zero state by the response signal for the request source, the number of which is not equal to n, then the counter 10 receives the binary code of the source served, and the device goes into the waiting mode. As soon as at least one request is received in register 1, a ready signal is generated at output 23,

by which the servicing device issues a trigger signal at input 24. At the same time, the analysis of the contents of register 1 is performed from the source number, per patient unit served in the previous operation cycle of the device.

Elements And 16 form the position code of the source number in those cases when, after issuing for service a request from

The i-ro source in register 3 has requests in bits 1 through / -i inclusive. In this case, after serving the request from the (source), a binary code of the number (/ - | -1) is generated in the counter 10 after the trigger 6 is set to the state "1

at the (/ + 1) th output of the decoder 11, a single signal appears, which through the elements OR 13i, ..., 13, opens the elements AND 16i, ..., 16, - + i through the first inputs. In addition, a single signal from the (/ - (- 1) -th output of the decoder 11 through the elements

OR 12, ..., elements AND 14, - + :, ..., 14 are opened. But since there are no requests in bits with (r + 1) -th for the lth registers 3, then at the output of the OR-NOT 15 element a single signal is generated, which

all elements of AND 16 are opened through the second inputs. With these elements, the position frame of the source number is then formed, which is transmitted through the OR element 17 to the inputs of the OR element 18 and the encoder 19. Next, the device works in the same way as before.

Claims (1)

Invention Formula A device for servicing requests containing the request register, the unit inputs of the bits of which are a group of device request inputs, the zero inputs of the request register are a group of device response inputs, the trigger whose unit input is the device start input, the AND element, the first OR element, the output is signal the output of the device, the delay element, the counter, the defragrator, the inputs of which are connected to the outputs of the counter, the first group elements AND, the first input of the i-ro element AND of the first group (, 2, ..., n, n is the number of sources of queries) is connected to the output of the rd bit of the query register, characterized in that, in order to increase speed, the encoder is entered into it, the outputs of which are the address outputs of the device, three groups of elements OR, the second and third groups of elements AND, the element OR NOT, the buffer register of requests, the element NOT, the block of elements AND, the second the OR element, the output of which is the device ready output, and the third OR element, whose inputs are connected to the response inputs of the device, the output of the third element OR is connected to the first input AND element, the first control input of the AND block and the zero input of the trigger, the zero output of which is connected to the second inputs of the AND elements of the first group, the outputs of which are connected to the single inputs of the same bits of the buffer register of requests, start input of the device connected to the counting input of the counter, - the engineering inputs of which are connected to the output of the block of elements AND, the second control of the upley input of which is connected to the output of the element NOT, the group of inputs of the block of elements AND connected to the outputs of the encoder, the single output of trigger The era is connected via a delay element with the control input of the descrambler, the first output of which is connected to the first input of the first element AND the second c-uppa and the first inputs of the OR elements of the first group, / -and the decoder output (,. 3, ..., l) is connected with / -th inputs from (/ -1) -th to (n-1) -th element OR of the first group, the n-th output of the descrambler is connected to the first input of the "-th element AND of the third group and the first inputs of the OR elements of the second group, (p-2) -and output of the decoder (, 2, ..., p-1) is connected to (2 + 1) -th inputs from the first to (p-2) -th elements OR of the second group, output of the 2nd element If the first group is connected to a first WMOs 5 Q 5 5 0 the home of the (2 + 1) -th element AND of the second group, the output of the 2nd element OR of the second group is connected to the first input of the 2nd element AND of the third group, the unit output of the / -th bit of the buffer query register is connected to the second input of i-ro the element of the second group and the second input of the / -th element of the third group, the inverse output of the gth bit of the buffer register of requests is connected to the (r - (- 2) -th input of the (r + 1) -th and subsequent elements of the second group and with (/ + 3) -th input (g + 1) -th and subsequent elements And the third group, the output of the g-th element And the second group is connected to the first input / -g the element OR of the third group and the r-th input of the element OR NOT, the output of which is connected to the third inputs of the AND elements of the third group, the output of the I -ro element AND of the third group is connected to the second input of the / -H element OR of the third group, the outputs of the elements OR of the third group connected to the corresponding inputs of the first element OR and the inputs of the encoder, the output of the nth element OR of the third group is connected to the input of the element NOT and the second input of the AND element, the outputs of the query register are connected to the corresponding inputs of the second element OR, the output of the AND element nen counter with reset input. About 1 p-1 Table 1 Oh oh Oh oh Oh oh About 1 Element number Signals output elements OR 12 cops and 1411 , L .....: L .. eleven 211 eleven n-11111 11111 T l b P and 17 3  --- Content Number of decoder outputs 11 counter. --J-- L.L.i. ::: .. 110000 / 21,000 oo p-110 P1 Table A Element number Signals output elements OR 13 Cops And 16: 111 11111 2111 eleven p-111 n1 table 2