SU1587517A1 - Device for addressing buffer memory - Google Patents

Abstract

The invention relates to computing and can be used to sequentially address memory cells of a buffer memory. The purpose of the invention is to simplify the device. The device contains counters 1, 3, 5, multiplexer 2, group of registers 4 1, ..., 4 N, register 6, decoder 7, elements OR 8 and 9, elements 10 and 11 of delay, synchronization input 12, inputs 13 data downloads , boot synchronization inputs 14, address loading inputs 15, address outputs 16, cycle termination output 17. The device allows, in data processing systems with a common field (block) of memory, to form a buffer memory access address, which can be either a constant and continuous part of a memory block, or a number of buffer zones spaced apart in a block memory data processing system. 1 il.

Description

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The invention relates to computing and can be used as a shaper of a buffer storage device for sequential addressing of memory cells.

The purpose of the invention is to simplify the device.

The drawing shows a block diagram of the device.

The device contains the first counter 1, multiplexer 2, second counter 3, group of registers 4, .. ,, 4, third counter 5, register 6, decoder 7, elements OR 8 and 9, delay elements 10 and 11, synchronization input 12, inputs 13 downloads of data, inputs 14 of synchronization of downloads, inputs of 15 downloads of addresses, outputs of addresses 16, and output 17 of a sign of the end of the cycle.

The device works as follows.

The device has two modes of operation, namely: the mode of loading the address of 1MY registers and the mode of formation

address addresses.

In the mode of loading into .group of registers 4 ,. .., 4 d. A record is made, the codes of the initial addresses of the zones of the memory block allocated for the buffer storage device and their information volumes, and the register 6 contains the code of the number of registers used in this exchange session

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In the loading mode of each of the registers 4 ,, ..., 4 and register 6, the inputs 13 and 15 of the device are set, respectively, the data loaded into the register, and its address, accompanied by a signal on the synchronization input 14 - 1 load. Data is written to the indicated registers by the outputs of the decoder 7. In each

group registers are written

the code of the starting address of the 1st, ..., nth zone of the memory block allocated for the buffer, and its information volume, and register 6 contains the code of the number used in this Exchange session registers 4, ..., 4p which is then rewritten by the signal on the synchronization input 14 by the passed OR 9 and delay 11 elements to counter 5. In this mode, the register loading sequence should be as follows: register 6, register 4 with the code of the start address and the volume of the first buffer zone, register 4 from ko

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home of the starting address and volume of the second. memory block zones, etc. In counter 1, the data (the code of the initial address of the buffer zone) is recorded by the signal from the input 14 of the load synchronization, which passed the element OR 8 and the element 10 delay. The same signal records the code of the information volume in the counter 3. After the loading mode is over, the device is ready for operation in the mode of forming the addresses of access to the memory block. The source for this mode is the state in which counter 5 stores the code for the number of registers 4, ..., 4p in the group, in counter 1, i.e. The address of the first buffer zone is set at the device’s address outputs 16, and the information volume of the first buffer zone of the memory block is set in counter 3.

If it is necessary to modify the address, synchronization input 12 receives a signal that adds one to the contents of counter 1 and reduces by one the contents of counter 3, in which the code of the current volume of the first buffer memory zone is recorded. The generation of subsequent address addresses for the first buffer zone is performed in the device in the same way.

Upon completion of the formation of the addresses of the first buffer zone at the output of the counter 3, a signal appears, which reduces by one the contents of the counter 5. At the same time, the output signals of the counter 5, affecting the address inputs of the multiplexer 2, are connected to the information inputs of counters 1 and 3 the signals of register 4, in which the initial code of the address and the information volume of the second buffer zone are stored respectively. The loan signal of counter 3 passes through the OR element 8 and the delay element 10 and writes into the counters 1 and 3, respectively, the starting address code and the information volume of the second buffer zone. The formation of the addresses of the second buffer zone and the transition to the subsequent buffer zones in the device are performed in a similar way.

Upon completion of the formation of the addresses of the buffer memory at the output of the counter 5, i.e. At output 17 of the control, a signal appears, indicating the end of the address generation cycle. This signal through the element OR 9 and the element 11 delay rewrites from register 6 to the counter

5158 5 code of the number of used registers of the group.

After writing to the counter 5 from the data register 6 by a signal from the output of the delay element 10 (by the signal of the counter 3 borrowing, passing the SHSh 8 and delaying 10 elements), the information volume and the initial address of the first buffer zone are recorded, respectively, counters 3 and 1,

For normal operation of the device, the magnitude of the propagation delays on elements 10 and 11 must satisfy the following conditions: the magnitude of the propagation delay of the signal at Element 11 delays must be greater than the signal duration at the synchronization input 12 (the duration of the counter 3 borrowing signal); the delay of propagation of the signal at the delay element 10 must be greater than the sum of the propagation delay times of the signals at the delay element 11, the counter 5 (according to the information inputs of the record) and the delay of operation of the multiplexer 2.

Claims (1)

Formula of invention e and N A device for addressing a buffer memory containing a decoder, a group of registers, a register, two OR elements, a first delay element, a multiplexer and three counters, an information input and a decoder synchronization input are connected to the device’s address load and device load synchronization inputs, respectively, the decrypt outputs 5 0 5 0 five 76 The rator is connected to the inputs of the register entry and group registers, the information inputs of which are connected to the boot input and the device, the outputs of the group registers are connected to the information inputs of the multiplexer, the first output of which is connected to the information input of the first counter, the output of which is the address output of the device, inputs The counters of the first and second counters are connected to the synchronization input of the device, and the inputs of the first and second counters are connected to the output of the first delay element, the input to The op is connected to the synchronization input of the device boot and with the first input of the second element OR, the information input of the third counter is connected to the register output, the information output of the third counter is connected to the multiplexer address input, characterized in that, in order to simplify the device, it contains a second delay element, the input of which is connected to the output of the second OR element, the second input of which is connected to the output of the cycle termination feature device and the loan output, the third counter, the recording input of which is connected to the output of the second delay element, and the input of the subtraction - with the input of the loan of the second counter and the second input of the first element SH, the counter input of the second pori5 counter is connected to the synchronization input of the device, and the information input of the second counter is connected to the second output of the multiplexer.