SU1383445A1 - Device for delaying digital information - Google Patents

Abstract

The invention relates to computing, in particular to storage devices, and can be applied to delay information transmitted in digital data processing systems. The aim of the invention is to expand the field of application of the device by providing data output in both forward and reverse order. The device contains an address counter 1, a switch 2, a drive 3, a counting trigger 4, an output register 5, a data output sequence control input 6, a synchronization input 7, information inputs 8 and outputs 9. The device provides a delay of data transmitted through the drive 3 during an address cycle time determined by the installation of the counter 1, if possible, in each cycle, read the data in reverse order with respect to the sequence of their recording, which allows the device to be used, for example, for fast Fourier transform. 2 Il.

Description

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The invention relates to computing, in particular to storage devices, and can be applied to delay information transmitted in digital data processing systems.

The purpose of the invention is to expand the field of application of the device by providing data output both in direct and in reverse order.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - timing diagrams for the operation of the device.

The device contains (Fig. 1) an address counter 1, a switch 2, a drive 3, a counting trigger 4, an output register 5, a data output sequence control input 6, a synchronization input 7, information inputs 8 and outputs 9.

On fis. 2 shows diagrams of clock pulses 10 at input 7, signals AND at the address inputs of accumulator 3, signals 12 at information inputs 8 and signals 13 at outputs 9 of the device.

The device works as follows.

At the initial moment of time, the counter 1 is reset (Fig. 1). To arrange a direct sequence of data output, input 6 is given a logical zero signal. In this case, the trigger 4 is held in the state of logical zero and the switch 2 passes the address from the outputs of the counter 1 to the address inputs of the accumulator 3 without change.

The delay of the information arriving at the inputs 8 in this case is carried out as follows (Fig. 2).

Signals 12 are fed to inputs 8, followed by clock pulses 10 of the "square wave at input 7" type, with the information recorded in cell 3 of the previous delay cycle being read during the first half of the clock cycle, and during the second half of the cycle writing information into this the same cell, the reading of which occurs in the next cycle of the delay. Counter 1 sequentially iterates over the addresses, recording the words arriving at jia inputs 8, into the cells of accumulator 3. For the n delay cycles, all n words are sequentially written, and n words of the previous array of information are in the same (right order) read from accumulator 3 . The read word in the register 5 is fixed by the falling edge of the clock pulses at the input 7.

If a logical unit signal is sent to the input 6, then the trigger 4 does not block in its R-way and at the end of the direct write and read cycle a score is issued

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the first signal of the end of the previous cycle, which switches the trigger 4 to the state of a logical one. In this case, the switch 2 switches the address outputs of the counter 1 in such a way that instead of addresses Co, GI, 02, ...., um-i, addresses ..., a, O, ao arrive at the address inputs of accumulator 3.

During the next delay cycle, the generation in the reverse order of the formation recorded in the previous cycle (read and write cycle in forward order) occurs. At the end of the information enrollment cycle, the flip-flop 4 is inverted again in the reverse order. Switch 2 skips the addresses again in direct order, while again reading and writing in the direct sequence.

Thus, reading in a direct sequence of information recorded in an inverse sequence, or reading in a direct sequence of information recorded in a previous cycle in an inverse sequence, i.e., in each cycle, information in the inverse (in relative to the sequence of the recording sequence, which allows the device to be used for solving problems of digital data processing.

Claims (1)

Invention Formula A device for delaying digital information containing an accumulator-address counter and an output register whose outputs are outputs of the device, the information outputs of the accumulator being connected to the information inputs of the output register, the control input of which, the write-read input of the accumulator and the count input of the address counter are combined and are a device synchronization input, characterized in that, in order to expand the field of application of the device by providing data output in both forward and backward sequences In particular, the device has a counting trigger and a switch, the control input of which is connected to the output of the counting trigger, the counting input of which is connected to the overflow output of the address counter, the bit outputs of which are connected to the information inputs of the switch, the outputs of which are connected to the address inputs of the drive, the information inputs which are the information inputs of the device, and the blocking input of the counting trigger is the input controlling the sequence of the device data output. i- / ra / fT L tact Thu 3/7 10 11 Adf) i-t XAdpi HaddrPTU: 12 lfffxi-fyC xi. iS DSb / x i-1 X 2 I X 2 l i / Figure 2