SU1524094A1 - Buffer storage - Google Patents

Abstract

The invention relates to automation and computing and can be used in information display devices. The aim of the invention is to expand the field of application of the device by making it possible to read information in the forward and reverse directions. The adder, the second multiplexer and the switch are entered into the device. It is possible to set the forward and reverse read start addresses. 1 il.

Description

The invention relates to automation and computing and can be used in information display devices.

The aim of the invention is to expand the field of application of the device by providing the ability to read information in the forward and reverse directions,

The drawing shows a block diagram of the device.

The device contains a memorized block 1, the first multiplexer 2, the counters of the 3 and read 4, the adder 5, the second multiplexer 6, the switch 7, The drawing also shows the echo 8 of the forward and reverse read start addresses, the read direction input 9, the input 10 of setting the starting address, the clock inputs of the write 11 and read 12, the input 13 of the write-read, the information input 14 and the output 15 of the device.

The buffer storage device (BZU) works in a slow way.

In the BZU, information is recorded in the storage unit 1 during the operation of the write address counter 3, the reading from the storage unit 1 occurs during the operation of the address reading reader 4. The address signals to the storage unit 1 are received through the first multiplexer 2, which supplies these signals during the recording from the counter 3, and during the reading from the counter 4.

In order for the address counters to work correctly, the 3 records should receive clock pulses only during recording (TI GP), and readout address counter 4 only during the reading (TI MF). Such a construction of an address address to the memory allows one to write information, fill the memory cells one after another, and the number of TI GP can be any, but not more than the number of cells of block 1. Such a record is similar to writing information into a shift register. Reading information format

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These can be produced by words of any length, but not more than the number of block cells. When reading in the forward direction, the starting address is determined by the code of the input number H8. When reading in the reverse direction (reverse), the starting address is determined by the code of the number at the input 8. The read direction is determined by the read direction signal, which controls the switching of the second multiplexer 6 and switch 7.

Reading in the forward direction. In this case, through the second multiplexer 6, the code of the number M 8 goes to the input of the adder 5, the binary input from the output of the counter 3 is sent to the other input of the adder 5, from which the code M 8 is subtracted, the result of the subtraction from the output of the adder 5 enters the information inputs of read counter 4 and determines the first cell of block 1, from which reading begins. The number of bits of information read from the memory is determined by the number of clock pulses of the TI SCH. For reading in the forward direction, the clock pulses of the TI MF through the switch 7 are fed to the +1 input of the read counter 4. When reading in the forward direction, signal 9 is chosen to be logical O, while reverse reading is logical 1. As a result, clock pulses TI MF through switch 7 are fed to input -1 of counter 4 of reading.

The ability to write the initial number into the read counter 4 and the further generation of addresses for the storage unit 1 allows the information to be read from the memory with the word of the desired length and in the desired direction. Since the recording of information in the memory can be done in portions of any length (but not more than the length of the storage unit), such a device can be used as a shift.

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Claims (1)

This register including reverse. Invention Formula The buffer memory is a device containing a storage unit, a write counter, a read counter and a first multiplexer, the first and second information inputs of which are connected respectively to the outputs of the write counter and read counter, the control input is the write / read input of the device, and the output is from With the address input of the storage unit, the information input and output of which is the Gc information input and output of the device, the counting input of the record counter is a clock input of the device record, ex In order to expand the field of application of the device by enabling information to be read in the forward and reverse directions, an adder, a second multiplexer and a switch, whose control input is the clock input of the device, are entered into it, the first and second outputs are connected respectively, with the forward and reverse counting inputs of the readout counter, the control input of which is the enable input for setting the device’s initial address, and the information input is connected to the output the first and second inputs of which are connected respectively to the outputs of the second multiplexer write counter, the first and second information inputs of which are respectively the inputs of the initial forward and reverse readout address of the device, and the control input of the second multiplexer and the information input of the switch are the input of the read direction the devices, the write and read inputs of the storage unit are connected respectively to the input of the write counter and the control input of the switch. Wl f / 5 IT l f IT  Mosp