SU842957A1 - Storage device - Google Patents

Description

(54) STORAGE DEVICE

one

This invention relates to memory devices. and can be used in measurement information acquisition systems as a buffer storage device.

The known memory device consisting of accumulators, address counters and control signal conditioners 1.

A disadvantage of this device is the low effective capacity.

The closest technical solution to the present invention is a memory device containing a memory matrix, an address counter, a circuit, a device operating mode selection, control-signal drivers 2.

The disadvantage of this device. the effective capacity is low, since it is necessary to record redundant information when storing the measurement results of a continuous function with a given error.

The purpose of the invention is to increase the effective capacity of the device.

The goal is achieved by the fact that a memory device containing a drive, an address counter and a control unit, the first output of which is connected to

the first control input of the accumulator, and the second output - to the input of the address counter, the information inputs and outputs of the accumulator are respectively the inputs and outputs of the device, the address inputs of the accumulator are connected to one of the outputs of the address counter, contains an overflow counter, an overflow register and AND elements, moreover, the overflow counter input is connected to another output of the address counter, the overflow counter outputs are connected to the first inputs of the AND elements and the overflow register inputs, the outputs of which are connected to volts And the third inputs of which are connected respectively with the address and second control inputs of the storage device.

The drawing shows a structural diagram of the proposed device.

The device contains a drive 1, an address counter 2, an overflow counter 3, an overflow register 4, AND elements 5 and a control unit 6.

Claims (2)

The information inputs and outputs of accumulator 1 are, respectively, the inputs and outputs of the device. Address inputs of the drive 1 are connected to one of the outputs of the counter 2 addresses. The first output of control unit 6 is connected to the first control input of accumulator 1, and the second output is connected to the input of counter 2 of the address. The input of the overflow counter 3 is connected to another output of the counter 2 addresses. The outputs of the overflow counter 3 are connected to the first inputs of the And 5 elements, and the inputs of the overflow register 4, the outputs of which are connected to the second inputs of the And 5 elements. The third inputs of the And 5 elements are connected respectively to the address and second control inputs of the accumulator 1. The device operates as follows in a way. When measuring a continuous function, when its instantaneous values are converted into a digital code, the storage device operates in the recording mode: the converted values are sequentially recorded in drive 1 cells, since the access enable signal is generated at each operation clock of the counter 2 addresses. In this case, the sampling rate of the measured function is minimal. An increase in the duration of the function in comparison with the minimum value causes an overflow of the counter 2 addresses, which is fixed by the counter 3 overflows and remembered by the register 4 overflows. A new cycle of accessing to drive 1 begins, with the aid of the elements 5 and the resolution signal being formed with even combinations of the counter 2 addresses. As a result, previously recorded information is stored in odd-numbered cells, while in even-numbered cells new incoming information is recorded with a double sampling rate. Subsequent overflows of the counter 2 addresses replace the redundant information in cells with odd addresses (3, 7, 11, etc.), then in cells with even addresses (4, 8, .12 ...), etc. ., with a corresponding increase in liiara discretization. The read algorq is determined by the discretization achieved in the write mode, the code of which is stored in the overflow register 4. As a result of reading, the measured function is represented by a sequence of numerical simulations, following with a discretization step achieved in the recording mode, which provides the specified relative approximation error, given by the number of discrete values characterizing the original function. In the proposed device, the effective capacity is increased in comparison with the known one by replacing the redundant information in the storage cells when the address counter overflows. Claims of Invention A storage device comprising a storage device, an address counter and a control block,. The first output of which is connected to the first control input of the storage device, and the second output - to the input of the address counter. the information inputs and / outputs of the accumulator are respectively the inputs and outputs of the device, the address inputs of the accumulator are connected to one of the outputs of the address counter, characterized in that it contains an overflow counter, an overflow register and elements AND, moreover, to increase the effective capacity of the device. the input of the overflow counter is connected to another output of the address counter, the overflow counter outputs are connected to the first inputs of the AND elements and the overflow register inputs, the outputs of which are connected to the second the inputs of the elements And, the third inputs of which are connected respectively with the address and the second control of the storage device. Sources of information taken into account in the examination 1. Zam ting N. I., Smolin D. A. Blocks of buffer memory in the CAMAC standard. Preprint. JINR, P10--9666. Dubna, 1976. 2. Damatov Ya. M., Nikityuk N. I. Semenov V. N. A semiconductor dynamic storage unit in the CAMAC standard, 1978, PTE No. 6 (prototype).