SU963099A1 - Logic storage device - Google Patents

Description

(54) LOGICAL STORAGE DEVICE

one

The invention relates to memory devices and can be used in systems of complex logical data processing.

A logical memory is known in which logical operations are implemented by simultaneously reading from two cells containing operands and from a third cell containing a constant, which is determined by the output. a) complete logical function l.

The disadvantage of this device is low speed when performing complex logical operations.

The closest to the proposed & - | 5 is a logical memory containing a drive with numerical lines on toroidal ferrite cores with PPK, flashed by write and read bit buses and linear write and read widths, with the drive connected to the bit outputs recording formmatters and to the amplifiers of the read amplifiers whose outputs are connected to regeneration register triggers, the outputs of which are connected to the first and second elements And the register, (the words whose inputs are connected to the inputs the OR elements, and the outputs through the bit elements AND and OR to the bit imagers of the record, the address elements AND, the same inputs of which are connected to the outputs of the decoder, others. to the outputs of the elements OR control, and the outputs to the address format wired, the OR element, whose inputs are connected to the corresponding control buses, and pulled out to the AND counterparts and to the inputs of one of the OR controls of the G 2.

A disadvantage of the known device is the low speed when performing operations of finding matching elements in arrays of information.

The purpose of the invention is to increase the speed of a logical storage device. The PSD is a goal achieved by the fact that a logical storage device containing a matrix of storage elements, write signal drivers, read signal generators, read amplifiers, word registers, address decoder, OR elements, and OR elements, and elements of AND, and outputs of the first register, the words are connected to the first inputs of the elements AND of the first group, the outputs of which are connected, to the first and second inputs of the elements OR of the first group, the outputs of which are connected to the inputs of the first generators write drives, the outputs of which are connected to the bit needles of the matrix recording, the read bit buses of which are connected to the first inputs of the read amplifiers, the second inputs of which are combined and the device's reset input, and the outputs of the second group OR connected to the inputs of the first register of the word, the output from the south-south of the elements OR of the third group is connected to the first inputs of one of the elements AND of the second group, the outputs of which are connected to the inputs of the second signal conditioner for Isi, outputs of which are connected to address buses of matrix recording, first input of element OR is connected to the first input of another element OR of the third group, whose output is connected to the first inputs of other elements AND of the second group, the outputs of which are connected to the inputs of readout shapers, which are connected to the address. matrix readout buses, the second inputs of the elements of the second group are connected & to the outputs of the address decoder, the outputs of the second word register are connected to the first inputs of the elements of the third group, the outputs of one of which are connected to the first inputs of the OR elements of the second group, the outputs of the other elements AND the third group are connected to the third inputs of the OR elements of the first group, and the second inputs to the first input of one of the OR elements of the third group, the second and third inputs of which are connected respectively the second inputs of one of the AND elements of the first group and the output of the OR element and the second inputs of the other AND elements of the first group, the second inputs of the OR elements of the second terminal, and the outputs of the read padders are information inputs and outputs devices, whose names ynpadfennroraHx whose inputs are the second inputs of one of the elements of the third group and the first and second inputs of the elements of the third group, the reset inputs of word registers are the reset input, devices, entered counter, address registers, comparison circuits, fourth , the group of elements is And, the fourth group of elements is OR, and the multiplexer of the address, with the first inputs of the first element of AND the fourth group and the first element OR of the fourth group connected to the first output of the second register- words, and the second inputs to the second you In the course of the second register, the first inputs of the subsequent elements AND the fourth group are connected respectively to the outputs of the preceding elements OR of the fourth group, and the second inputs are connected to the corresponding outputs of the second word register, the first inputs of the subsequent elements OR the fourth group are connected respectively to the outputs of the previous elements AND the fourth group, and the second inputs are connected to the corresponding outputs of the second word register, the outputs of the address multiplexer are connected to the inputs of the address decoder, and the inputs are connected to with the counter outputs and one of the address register outputs, the other outputs of the first address register are connected to the inputs of the first comparison circuit, the inputs of the second address register are connected to the inputs of the second comparison circuit, the address inputs of the counter are address inputs of the device, reset inputs and control inputs of the counter and the address registers are the other reset inputs and other control inputs of the device, the outputs of the comparison circuits and the output of the last OR element of the fourth group are the indicator outputs of the device Twa. FIG. 1 shows a functional diagram of the proposed device; Fig. 2 illustrates an example of step-by-step finding matching columns of an array of information, which explains how the device operates. The proposed device contains (Fig. 1) a charger 1 with numerical lines 2 on toroidal cores 3 with a rectangular loop of preeclampsis penetrated by bit buses 4, bit bits Shvdamn 5, read, address and write b, and address buses 7 read, the first rolls 8 recording signals, the first group of elements OR 9, the first group of elements AND 10, the first register 11 words on the trigger 12, the input 13 is reset, the second group of elements 14 with information inputs 15 of the device, OR 16, the inputs 17-21 of the control the third group of elements OR 22 a meter 23 with reset inputs 24 and control 25 and address inputs 26, a first address register .27 with control inputs 28 and 29 for storing (no direct address code, a first comparison circuit 30, a second address register 31 for storing inverse address code, with control inputs 32 and -33 and reset input 34, embedded comparison circuit 35, address multiplexer 36, address decoder 37, second group of elements AND 38, second () setters 39 of write signals, read signals 40, amplifiers 41 touch van with entrance 42 strobe , the second register 43 words on triggers 44, designed to regenerate information in the device, with reset input 45, one of the third group AND 46, the third group of OR 47 elements and the other 48 elements, a third group of control inputs 49 and a fourth elements And 50. In FIG. 1, informational 51 and indicative 52 - 54 outputs of the device are indicated. FIG. 2 will give an example of step-by-step matching matching columns of an information array having six columns and recorded in the first five numerical rulers of accumulator 1. The four subsequent numerical rulers of accumulator 1 are a stack. FIG. Figure 2 shows an example of the coincidence of the first and third columns of the information array, as well as the coincidence of the second, fifth, and sixth columns; in fig. 2a, the initial data array, in FIG. 2 b d - consecutive steps to search for matching columns. The capacity of accumulator 1 is equal to N + 3/4 n (where n is the number of bits, N is the number of numerical lines necessary for storage processing the south array of information. During operation of the device, N numerical lines 2 of accumulator 1 are used to store the results of array processing. Later these numerical rulers are called a stack. The device works as follows. In the proposed device, elementary logical operations (disjunction, interdiction, etc.) are executed in the same way as in the well-known. l are: On nekotorsyu

Claims (2)

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