SU485501A1 - Associative logical storage device - Google Patents

Description

(54) ASSOCIATIVE LOGICAL STORAGE DEVICE

one

The invention relates to memory | devices (memory)

An associative logical memory containing numerical lines made of magnetic cores stitched with numeric write, read and read buses connected to address write, read and match indicators, respectively, and bit write, read and read buses, respectively, is known. to each of the read write drivers and read amplifiers, respectively, a sign register whose outputs are connected to information inputs of address circuits AND, a word register connected to the mask register Which outputs The discharge through the AND and OR circuits connected to respective discharge dnym shaper LM writing and reading controlling guides tires and tire reset.

These memories are built on elements, memory with an extensive magnetic core, the production of which has been mastered enough. In addition, for storing one bit of information at-j

vary by two transfluxors and a large amount of equipment is required per

bit chains

The purpose of the invention is to simplify the operation of the device and increase the reliability of its operation.

The proposed storage device differs from the known one in that it contains delay circuits, additional AND, pairs of OR circuits and regeneration indicators - by the number of numerical lines, one input of each additional AND circuit is connected to one of the control buses, the other to the output of the corresponding IJ regenerative indicator and the output to the input of the circuit of the gate and the input of one of the I.PI pair of circuits, the other inputs of each pair of OR circuits are connected to the outputs of the corresponding address circuits AND, and the outputs to the inputs of the write and read address drivers, one input of each indi Ator regeneration is connected to the corresponding word schine reading, and others - to schine reset.

The drawing shows a functional diagram of the proposed associative logic memory. The device contains a drive 1 with numerical lines 2 on magnetic cores 3, flashed by read bit buses 4, read write buses 5, read bits 6, read numbers 7, read numbers 8, and read numbers 9, the digits write drivers 10, bit drivers 11 readings, bit circuits 12 OR, bit circuits AND 13, mask register 14, register 15 words, reset bus 16, inputs 17., control buses 18-25, delay circuits 26 and 27, circuits 28 OR, address formers 29 records, address formers 3 0 reads, OR circuits 31, delay circuits 32, AND 33 address circuits, OR circuits 34, feature register triggers 35, feature register 36, reset bus 37, feature register inputs 38, read amplifiers 39, gating bus 40, read amplifier outputs, regeneration indicators 42, reset bus 43, additional circuits, coincidence indicators 45, spheres bus 46, bb) 1 inputs of 47 match indicators, reset bus 48. The control input of each additional circuit AND 44 is connected to the control bus 19, the information inputs to the output of the corresponding regeneration indicator 42, and the outputs of the additional circuits AND 44 to the input of the delay 32 and the input of one of the pair OR 31 others the inputs of each pair of OR circuits 31 are connected to the outputs of the corresponding address circuits AND 33, |, and the outputs to the cares of the write address reading and reading drivers 30. The information inputs of the regeneration indicators 42 are connected to the corresponding read digital buses 9, and the control inputs - to the bus 43 Sat dew. The device works as follows. In the initial state B, the word register 15 stores the input word X (Xi, ... X ;. ... Xfj), and in each line 2 of drive 1, some word Y is stored.) YtiV Mask register 14 is in the state where the I-bit of the input word is allocated, and the regeneration indicators 42 and the match indicators 45 are in the state O. The logical operations J that can be implemented in the proposed memory are performed when control signals are fed to the bus 18-425 . The associative search operation is implemented as follows. The implementation of an associative search operation in this memory is based on performing an unequal operation one bit over the input word and arbitrary viacijHBOM words stored in the accumulator. The logical inequality operation is implemented in two tnDta scopes to the charger. In the first cycle cycle, when a control signal is applied to the bus 22 on the output reading number buses 9, a signal Z- (i,) XVL is generated, which is fixed on the regeneration indicators 42 and the match indicators 45, and the cores 3 numerical lines 2 go to Qi (t,) Xj V Yi, in the second cycle, under the action of signals from the output of the delay circuit 27, the cores of the 3 numerical arrays go to, (i,.) X, and on the output bus 9 of the reading, the signal corresponding to Z (t tt) y X Thus, in one of the two cycles of the first cycle of accessing the charger on numerical values Ach 9 reading selected numeric lines 2 appears the signal corresponding to the execution of the comparison operation (, th bit of the input word with the I th digit of each of the words stored in the selected j numeric lines 2, since Zi (t, vZi (t, T) Xiyi VX; Vi. The regeneration indicators 42 and the match indicators 45 record the result of the comparison in the I-th bit, and if the symptoms in this bit do not match, the regeneration indicators 42 and the match indicators 45 of the corresponding numerical lines 2 are switched to the state 1. Each of the interrogated cores of 3 t go de d nnyh numerical linevk 2 are state corresponding to the result i (t, + T) x; .. The regeneration operation is also performed in two cycles when the signal is applied to the control bus 19 in the regeneration cycle. At the same time, in the first cycle of this cycle, when a signal is applied to the control pad 19, under the action of this signal, the valves 44 are polled, from the outputs of which through the circuits 31 OR to the inputs. the address shaper 29 of the record passes the excitation address signals if the regeneration indicators 42 are in state 1, i.e., j, th. The resolution of the selected numerical ruler 2 generated a mismatch signal VXy. At the same time, through the control circuit 28, from the inverse outputs of the register 15, the discharge signals Xj 1 are passed through the mask register 14, the bit circuits AND 13 and the circuits 12 OR OR to the inputs of the bit shaper 10 of the recording. The core 3 of the polled number lines 2 are transferred to the state. X-V Y; , and on the output numeric tires JI 9, the read signals Z; {t,) (.), which confirm the states of the regeneration indicators 42 and co-op indicators 45, are induced. In the second cycle of the second access cycle, through the time determined by the delay circuit 26, its output appears signal under the action of which from the direct output of the i / th bit of the register 15 words, if it is in the state, through the register 14 of the mask, the allocation of the th discharge, through the bit circuits And 13 and schemes 12 ICHs at the inputs of bitformers 11 readouts pass through the excitation signals Xj 1. One temporarily, from the outputs of the delay circuits 32, the address formers 30 of those numerical lines 2 are excited through the circuits 31 OR, the regeneration indicators 42 of which are in the I states. The L-th bit of the selected number lines 2 goes to the initial state Q; (to i) Y;, and on the number lines 9 reads the signals Z; (t, - ") which confirm the states of the indicators 42 to 45. After performing a comparison operation of J, th bit of input A word with the i-th bit of each of the selected words is provided by the regeneration indicators 42 when a signal is sent to the control bus 43 is reset to the state O, and in the match indicators 45 the results of comparing the values of the i-th bits of the input word and each of the words stored in the numerical lines 2 of the accumulator 1. In the same way, the operation

60 I comparisons in the remaining (ft - 1) bits of the words being compared. After performing the operation of comparing the input word with the array of words stored in the accumulator, the match indicators 45 are interrogated. At the same time, at the outputs 47, signals appear only from those indicators that remained in the initial states, i.e., the code in this numerical line 2 coincided with the code of the input word. The subject of the invention is an associative logical storage device containing numerical lines made on magnetic cores stitched with numeric write, read and read buses connected to address write drivers, read and match indicators, respectively, and bit write, read and read buses connected to the bit shaper of writing, reading and reading amplifiers, respectively, the register of the sign, the outputs of which are connected to the information inputs of the address circuits And, the register with connected to the mask register, the outputs of which through the bit circuits AND and OR are connected to the corresponding bits of the write and read drivers, control buses and reset buses, characterized in that, in order to simplify the device and no-f increase its reliability Work, it contains delay circuits, additional AND schemes, pairs of OR schemes and regeneration indicators - by the number of numerical lines, one input of each additional AND scheme is connected to one of the control buses, the other to the output of the corresponding regenerant indicator and, the output to the input of the delay circuit and the input of one of the ijapbi OR circuits, the other inputs of each pair of OR circuits are connected to the outputs of the corresponding address circuits AND, and the outputs to the inputs of address write and read drivers, one input of each regeneration indicator is connected to the corresponding numeric reading bus, and others to the reset bus.