SU1183986A1 - Device for prompt checking in automatic control systems - Google Patents

Abstract

1. DEVICE FOR OPERATIONAL CONTROL CONTROL CHCTEbiAX AVTOMATIZM- Rowan, comprising a register, an input unit of information, the first outputs are connected to first inputs of the control unit, -Connection first outputs to the unit memory vpsodom second - to the first input of the indication unit, wherein that, in order to simplify and improve the speed of the device, two elements are introduced into it OR, a BAN element, an adder and an address counter, the first inputs of which are connected to the third outputs of the control unit, the second input from the second m output of the information input unit, and the output - with the second input of the memory unit and through the first element OR - with the second input of the display unit - the third output of the information input unit is connected to the third input of the memory unit and through the second OR element - to the register input, the output of which is connected to the first input sum (L of the torus connected by the second input to the output of the memory unit, the first output to the second input of the control unit, and the second output to the second input of the first IPI element and through the BANNER element to the second input of the second OR element). 00 O9 CO 00 about

Description

2. The device according to claim 1, characterized in that the control unit comprises first and second pulse counters, two triggers, the first AND element, the first OR element, the first delay element, the second AND element and the second OR element, as well as the third element OR, the first trigger, the third element AND, the fourth element OR, the second element of the delay, and the fourth element AND, the output of which is connected to the third output of the control unit and through the first pulse counter to the second input of the second the OR element whose output is connected to the output of the control unit and through the second pulse counter to the first input of the second trigger and to the first input of the third OR element, the second input

connected to the corresponding first input of the control unit, the output of the second trigger is connected to the second input of the first element And the second input is connected to the input of the control unit, the first output of the third trigger is connected to the second input of the second element And, and the second output to the second input of the fourth element And and the input is with the corresponding first input of the control unit, the third input of the second element OR is connected to the corresponding first input of the control unit, the second inputs of the first and fourth elements OR are connected to the corresponding first m outputs of the control unit and to outputs of the first and third AND elements, respectively, the second output of the first flip-flop is connected to the second output of the control unit.

I

The invention relates to computing and can be used as a device for technological or production processes, equipment status, operational control in a control system, in the field of traffic management, to control the progress of network work, and also to display the conversion of task information. optimal planning.

The purpose of the invention is to simplify the device and increase its speed.

FIG. 1 shows a functional diagram of the device; FIG. 2 is a diagram of a torsion block; FIG. 3 block input information. The device contains an information input block 1, an address counter 2, a control block 3, elements OR 4 and 5, a memory block 6, a register 7, an adder 8, an indication block 9, a prohibition element 10.

The control unit (Fig. 2) contains counters 11 and 12 pulses, elements OR 13-16, elements AND 17-20, triggers 21-23, delay elements 24 and

25, a pulse generator 26, as well as inputs 27-31 and outputs 32-36.

Information input unit 1 (Fig. 3). contains a photo-reading unit 37, a register 38 for short-term storage of the address, elements AND 39, AND 40, OR 41, OR 42, a control panel 43, a signal conditioner 44.

The button assignment is as follows: h button for selecting the direct or transposed matrix mode; 5 - a set of buttons for setting the starting address, the button for recording the starting address; g button to turn on the mode Write to memory 9 - button to turn on the mode Read. RAM.

The reading of information from the photo-reading unit 37 is synchronized by the clock signals. Elements And 39, And 40 provide the transfer of the read information in the direction of one of the outputs, depending on the specified mode.

All specified blocks and elements are implemented on the basis of typical ones. For example, K565RU2, K155IE7, K155IE5, K155IR1 K155IMZ, K155TM2, K155LAZ, K155LE1, etc. can be used as a memory device, counters, register, adder, triggers, elements AND, OR 3. IMG-1-03. The input unit contains a console for manual input of information, as well as a photo reader FS-1501. The device works as follows. In the mode of recording the C-indices, the addresses of the cells of the memory 6 receive the addresses of the cells formed by the counter 2 addresses. The address information is fed to the input of the counter 2 of the address from the input unit 1 and is written to the address counter by the signal from the output 32 of the control unit. This signal is generated in the input block, fed to the input of the address counter through the control element OR 13. The information C- comes from the input unit to the information input of the memory unit 6 in tact with the recording signal occurring at the output 34 of the control unit. If the indices are to be presented in the form of a direct matrix, then the address of the first page of the block is first recorded in the address counter, and then the addresses of all cells of this page are formed by adding the unit address to the counter. When working with a direct matrix, the trigger 21 of the control unit is in the zero state, therefore the element AND 17 is closed and the element 18 is open. The recording signal from the output of the input unit enters input 29 of the control unit, sets the trigger 22 of this block to one and opens the AND 19 element. The clock pulses come from the output 34 of the control unit to the recording input of block 6 and simultaneously through the OR 15, delay 25 , And 18 arrive at the input of the addition of the unit of the address counter and the input of the counter 12. Each clock pulse records the indicator С ;.- in the selected cell of the memory block 6 and forms the address of the next cell, i.e. adds one to the address counter. The filling of the counter 12 occurs simultaneously with the enumeration of all the cells of the specified page. When counter 12 is filled, the signal from its output through the element OR 13 writes the address of the next page into the counter and adds 864 units to counter 11. After that, counter 12 is zeroed (zero chain is not shown). The information is recorded in the next page cells in the same way. When all the pages of the memory 6 are full, the counter 11 also fills and supplies a signal that switches the trigger 22 to the zero state. Recording information is over. When entering information with simultaneous transportation of the matrix of indicators, the address of the first page of the block is first written to the address counter. The information is recorded in the cell of the memory block corresponding to this address. Then the page numbers are alternately switched. To record information while transporting the matrix, trigger 21 is switched to a single position by a signal from the output of the input unit. Element And 17 is open, and And 18 is closed. The output signal of the input block trigger 22 switches to a single position and opens the element AND 19. Clock pulses arrive at the recording input of memory block 6 and through the elements OR 14, delays 24, I17, OR 13. enter the recording input of the address counter and the counter input 11. Each clock pulse writes information to the first cell of the selected page of memory block 5 and writes the address of the next page to the address counter. The filling of the counter 11 occurs simultaneously with the enumeration of all the pages of the memory block 6, therefore after recording the information in the cell of the last page of the memory at the output of this counter, a signal appears that switches the trigger 22 to the zero state. A matrix of indicators filled in this way will be transposed with respect to the original one. In the address search mode by indicator С-; the trigger 23 is switched to a single state by a signal from the output of the input unit. Element I 20 opens and the clock pulses come from the output 35 of the control unit to the read input of the memory unit and simultaneously arrive at the input of the addition of the unit or the input of the record of the page address depending on the position of the trigger 21. The readable information enters the input of the first term of the adder 8. At the input of the second term of this adder is the reverse code

of the compared indicator Cif previously written to register 7 from the input block through the element OR 4. The totalizer in this case works as a comparison circuit, which is provided by applying a signal to the control input of the prohibition element 10 and to the transfer input of the zero bit of the adder (not shown). When the readout from the memory block of the indicator coincides with that recorded in register 7, a single signal appears at the transfer output of the last bit of the adder, which enters input 31 of the control unit and switches the trigger 23 to the zero state through the OR 16 element. Element I 20 closes prohibiting clock pulses. The address of the memory cell from which the information was read in the last cycle is output to the display unit. At the same time, elements 24 and 25 provide a delay in writing the new address to the address counter until the process of writing or reading the memory block and transferring the information to the indication block is completed.

If necessary, sum up

indicators C., in rows or columns of the matrix, i.e. by the same name

Since all pages or all cells of a single page, the address information is generated in the same way as building a transposed or direct matrix, respectively, with the reading pulses of the memory block synchronized with the change of addresses. The information read from the memory unit is fed to the input of the adder, which in this case works as accumulating. This is provided by removing the signal from the control input element 10

prohibition and input transfer zero discharge adder. In the process of summation, information is accumulated in register 7 (the chain of records in the register is also not shown).

After reading all the addresses, trigger 23 is zeroed by a signal from counter 11 and information is output from the adder to the display unit.

When solving problems of sorting data that require selective recording and reading of information in a memory unit, this device allows time gain in comparison with the known one. This is possible due to the address access to the desired memory page organized by the address counter. In a known device, all rows and columns of the Memory Block Matrix are accessed only sequentially using shift registers, which excludes the possibility of selectively accessing the desired row or. column.

The input unit performs standard functions and does not require a detailed description. In the simplest case, it contains keyboards for typing information and typing the address, buttons for writing the address to the address counter and writing information to the memory block, buttons for reading the memory block, setting the record mode for records in the form of a direct or transcribed matrix. In the address search and summation modes, the output of address information from the input block to the address counter is clocked by a clock generator (not shown).

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Claims (2)

1. DEVICE FOR OPERATIONAL MONITORING IN AUTOMATIC CONTROL SYSTEMS, comprising a register, an information input unit, the first outputs of which are connected to the first inputs of the control unit, connected by the first outputs to the memory unit, the second output - to the first input of the display unit, characterized in that, with In order to simplify and improve the performance of the device, two OR elements are introduced into it, a BAN element, an adder and an address counter, the first inputs of which are connected to the third outputs of the control unit, the second input to the second output ohm of the information input unit, and the output - with the second pass of the memory unit and through the first OR element - with the second input of the display unit, · the third output of the information input unit is connected to the third input of the memory unit and through the second OR element - to the register input, the output of which is connected with the first input of the adder connected by the second input to the output of the memory unit, the first output to the second input of the control unit, and the second output to the second input of the first OR element and through the BAN element to the second input of the second OR element. SU .... 1183986> S 2. The device according to π. 1, characterized in that the control unit comprises a first and second pulse counter, two triggers, a pulse generator connected in series, a first AND element, a first OR element, a first delay element, a second AND element and a second OR element, as well as a third OR element connected in series , the first trigger, the third AND element, the fourth OR element, the second delay element and the fourth And element, the output of which is connected to the third output of the control unit and through the first pulse counter to the second input of the second OR element, output which is connected to the output of the control unit and via the second ₀ pulse counter - to the first input of the second flip-flop and to a first input of the third OR gate, a second input connected to a corresponding first input of the control unit, the second latch output is connected to the second input of the first AND gate and a second input - to the input of the control unit, the first output of the third trigger is connected to the second input of the second element And, and the second output to the second input of the fourth element And, and the input to the corresponding first input of the control unit, third input d of the second OR gate coupled to a corresponding first input of the control unit, the second inputs of first and fourth OR elements are connected to respective first outputs of the control unit and to outputs of the first and third AND elements, respectively, the second output of the first flip-flop is connected to the second output of the control unit. I