SU429467A1 - L \ NGAZINO STORAGE DEVICE - Google Patents

Description

This invention relates to memory devices. A known zaiamin device (ZU), containing a storage device connected to the number register, a register of the current free memory cell, is 1 connected to the register (last occupied by the memory cell, control unit, circuitry I.) However, the known device It has limited functionality. For example, it cannot be used to endorse such a mode of operation, when the first word read in the memory is also read first. The device does not provide a two-way access capability, nyu. array (| according to character-m-the first recorded word is read either the last or the first). In addition, the well-known memory has the ability to organize m-and-channel work but independent channels,; does not allow, if necessary, to organize the i Kapal (zh-informational arrays) in one common channel (array) or the dismemberment of any channel into / .independent channels. The need to organize the specified modes of store storage occurs when building translators, with the structural interpretation of algorithmic language s, with the dynamic distribution of the useful volume of the memory, with the internal sorting of information, with the organization of “queues in the computational process, when working with pencakes and in other cases. The described storage device differs from that known in that it contains the register of the first occupied memory cell, connected by two-way communication lines to the register of the current free memory cell, the AND circuit and the register of the last occupied memory, and the mode of operation, the input of which is connected to the control unit, and the output - to one of the inputs of the AND block, the outputs and the other input of which is connected to the drive and the number register. This embodiment allows you to extend the functionality of the device. , On fit. I shows the block diagram of the magazine; pas figs. 2 - memory cell structure. The minder device contains the register I / of the last occupied cell (PL), register 2 of the current free PL, register 3 of the first PL, block 4 of the AND circuits, register 5 of the operating mode, register of the 6th number} | akopitel 7, block manager 8. At the same time, the register 3 is connected by means of two-way communication lines to the registers f, 2 and block 4 of the circuits I. The input reg 1stra 5 is connected to the control unit (not shown in the drawing), and the output is

to one of the inputs of block 4, one of the outputs of which is connected to the hopper 7. The register 6 is connected by two-way communication lines with the block 4 and the hopper 7.

The memory cell consists of three parts. The first 9 is for the storage of a forward address (.PA) corresponding to Step 1 of the A mode (the first entry word is read first), and the -pasMeTiKH (AP) addresses; the second is W for storing information layers (ICs). the third is // for storing the return address (OA) corresponding to mode B (the first recorded word is (Last is read).

The storage device operates as follows. (Before starting work, the marking of the YP of the accumulator 7 is made. In register 5, a code corresponding to the operation mode is set. As a result, the marking in the PA of each free YAL indicates the address of the next free PL. In the process of further work with the proposed device and the need for marking is dropped .

The modes of operation of the stack memory are set and stored in register 5, which is controlled by a block. 4 circuits P, providing the required information circulation in the memory.

Mode A (the first recorded word is read first).

The recording of the IC in the stack memory is always performed at the address contained in register 2, and is carried out in two steps - writing the IC and writing the PA and the PL.

The contents of the PL, corresponding to the address in register 2, is read into register 6. When regenerating, the information module of the PL informs the IC, and in the PA it reads "O. At that, the contents of register 2 (transferred to register 3 (this transfer is carried out once and is necessary at the moment of formation of the information array) and to register 1, and the contents of the AP register 6 is transferred to register 2. Then, the contents of the register 5 are processed. If there is a sign of the record "Mode L" in it, then before being taken to (BP from the eating IP, it is accessed to the address stored in the register /. The contents of this PL are read to register 6. When regenerated. The user agent is restored from the registrar 2, JS-from the register 6. In the oip The OTRBHOM case takes you up to the next working hours regime.

Thus, when writing 1. information in the memory in mode L, the registers .1, 2 indicate the new values of the last st one and the current free PL, register 5 indicates the value of the first PL, and in PA the PL indicates either the address the next one is the PL or the bullet address.

Reading the formatting from the stack of the memory is always performed at the address contained in register 3. The contents of this PL are transferred to register 6. When restored, the information part is reset to zero, and the AP is restored from register 2. When the contents of register 5 are transferred to register 2, and the user agent from register 6 enters register 3.

Consequently, when reading information from the memory containing registers 3, 2 v (PA PA, the reading of which indicated, indicate the new values of the addresses occupied by the first, current free, and the address of the next free PL should be in the AP.

Mode B (the first recorded word - .lext is read).

Reflection to memory is carried out similarly to mode L.

Mode C (two-way access to the same information array).

Recording of an IS in a memory is made in the same way as recording information. In the L, IB mode, there are two methods: recording the IC, OA, and writing the PA and the PL. The difference is in the need to write OA in the PL, which is restored from the register during regeneration.

Thus, when writing ICs to a memory in mode C, registers 1, 2, 3 VI PA PL indicate the same values as in mode L, and OA indicates the address of the previous occupied PL.

The readout of the IC from a memory device, depending on the sign stored in register 5, can be performed either at the address contained in register 3 or at the address contained in register /.

Reading the information from the memory in mode L is carried out similarly to that described with the difference that after the selection of the IC from the memory is necessary in the OA, the new value of the first PL is written 0. This is done in the following way: ( The memory at the address contained in register 3. The register 6 reads the contents of this PL, the OA is reset to 0. During regeneration, information is restored into this PL from register 6.

When reading information from the memory in B after the completion of the selection of the IC from the memory, it is necessary to write to the user of the new value — the last occupied Ya.P. To do this, the memory is addressed to the address contained in the registry. The register 6 reads the contents of this PL, the user agent is reset to -nul, and the new contents of this register is restored to the same PL.

Thus, when reading information .113 З.У in mode C, the registers /, 2, 3 indicate new values of the last occupied, current free and first primary PL, and in the AP the AP, from which the reading was made, indicate the new values of the following free PLs. After sampling from the memory of all the ICs, the content of the registers /, 3 is reset to zero, and then dO | K. The layout of the memory, in general, does not coincide with that which was before the formation of the information array. In register 2, the address of the current free PL is entered. Mode D (m-notocale work on n independent channels).

If it is necessary to use the proposed storage device over several N independent channels, the following cases are possible:

a) all L independent channels work only in one of the considered modes (A, B, C). In mode B, odi-n register 26 is used, and .reg / is broken up into N parts.

In modes A, C, one register 2 is also used, and registers 1, 3 are divided into N parts, each of which corresponds to one specific cue and is used independently of the others.

b) all N channels work IB different modes. In L, B, C modes, OD.-IN register 2 is used, register / is divided into PA + Pz + ps, and register 3 into PA + ps parts, where PA, Pv, ps is the number of channels operating in modes A, B, C.

Information for writing to the memory and requests to read from it can come in any sequence through various channels. The number of registers 1, 3 can be reduced to one, common to all N channels. For this purpose, yV PLs are allocated in the memory for storing the addresses of the first jam, the last PL in the software for each specific channel. When each channel is connected, the contents of these cells are read into register 6 and, depending on the mode of operation stored in register 5, are transferred and registers 1, 3 or register /. At the end of the i-ro channel, the contents of these registers are entered into the same fixed PLs, whose addresses are determined by channel numbers.

E mode (channel coupling).

.If it is necessary to organize coupling i of any independent channels (information arrays) into one common, two main cases are possible:

a) alignment of the end of the i-th channel to the beginning of the t-TO channel. In this case, if the interlocking channels operated in mode A, or in mode C, or the / -Y channel operated in mode C, and the rth mode worked in mode A, then the address is addressed to the address in register 1 / -, When the channel is regenerated in the PA, the address from the register of the 5th i-ro channel is restored, and for channels operating in mode C, in addition, the address containing the register in the 3 rd channel is recalled. The PL recovers the address from the register of the 1 / th channel, the contents of the register of the 3th i-ro channel and the register of the / / -th channel (except the channels operating in different modes) is reset to zero, and the contents of the 3rd / -th channel register is transferred to the 3rd register of the 1st channel.

6} attachment of the beginning of the i-th channel to the end of the i-ro channel. In this case, if the interlocking channels operated in the same modes, and also the / -Y channel operated in the B mode, and the f-th in the A mode, then the memory is accessed at the address containing in the / i-ro channel register , during regeneration in PA YAP

the address from the register of the 3 j-.ro channel is restored, for channels operating in different modes A and B, the address is restored from the register of the / / -th channel, and for channels operating in mode C, in addition, the address is addressed to, contained in the 3 / pgo channel register, during regeneration in the OA PL, the address is restored from the register} of the i-ro channel. The contents of the register of the i-ro channel, the register of the 3rd / -th channel and, moreover, the contents of the register of the i-ro channel operating in mode B are reset to zero, and the soda press of the register of channel 1 is transferred to the register / i-ro channel; register contents

3 i-ro kaiala working in L mode is transmitted to the i-iro channel register.

Coupling channels operating in mode

B, without a preliminary review of their contents on the subject of detection of nerves occupied by PL, is impossible.

It is possible that when the beginning of the / th channel, which operated in mode B, is attached to the beginning of the i-canada, which worked in mode

C. To do this, a call is made to the address contained in register 3 of the i-ro channel, when regenerating, the address from the channel register is restored, the contents of this register are then nullified.

If necessary, cordon off several

Channels' leached operations are repeated with the only difference being that under the concatenated channels, they can already be understood not only by individual channels, but also by the combination of channels.

Mode F (channel division).

If it is necessary to divide one (any) channel into n independent channels, two cases are possible:

a) the dissected channel worked in one

of the modes (A, B, C). In this case, the division of the channel can be carried out anywhere.

In L mode, an address is specified (denoted by its address A), indicating the end of the i-ro

channel, and calls are made to the memory at this address. The content of this PL is read into register 6. And in the course of regeneration, the PA is reset to zero. Then the contents of the register} i-ro channel is transferred to register 1

(i + l) -ro kat.al, address X is transferred to register 1 of the i-ro channel, and the contents of the PA of register 6 are transferred to register 3 (i-i-l) -ro of the channel. In mode B, the memory is accessed in the same way as mode L.

the register 6 is read, and when the regenerate is in the same PL, the OA is reset to zero. The content of the OA register 6 is transferred to the register of the (i-f 1) -th channel.

In mode C, channel splitting is carried out similarly to mode L, with the difference that the address is made to the address contained in channel register 3 (i-bl) -ro. The contents of this PL is read into register 6 and, with the OA insert attached, it is scanned in

zero.

6) the dissected channel worked in various modes. There may be two situatsi.i.

The first - the channel sharing point is inside that part of the channel, which operates in any of the modes A, B, C. The sequence of operations is analogous to the stated. The second situation - the place of the channel section is located on the border of the parts of the canal operating in different modes. At the same time, if the channel being divided consists of parts operating in modes A and C, the sectional place is located at the end of the part of the channel operating in mode L. The sequence of operations is similar to the division of the channel operating in mode L.

If the cross section occurs at the end of the part of the channel that operates in mode C, then the address is stored at the address stored in the / (t-bl) -ro channel register. The contents of this PL are read into register 6, when being restored at the same address, the user agent is reset to zero, and the contents of the channel’s 3 i-.ro register are transferred to the register 3 {t + l) -: ro of the channel, and the contents of the user register’s register 6 transmitted to register 3 of the i-ro channel;

If the partitioned channel consists of parts operating in modes B, C, then the channel cross section is located at the beginning of the part of the channel operating in mode B, which is addressed to the address contained in the 3 r-channel register. The contents of this PL are read into register 6, during regeneration into the same PL the OA is reset to zero, and the contents of the OA register 6 are transferred to register 1 of the (i + 1) -th channel;

if the channel cross-section is located at the convex part of the channel that operated in mode B, then luo is addressed to address X. The contents of this PL are read into register 6, etc., and the return to the same PL OA is reset to zero, and the contents of register 1 The i-iro channel is transmitted to the register of the / (tll) -ro channel, and the contents of the OA register b are transferred to the register 1 of the f-ro channel;

The eCviH partitioned channel consists of parts operating in mode A, B, and the channel cross section is located at the end of the part of the channel operating in mode B and is addressed to address X. The contents of this PL are read to register 6, when restored to that while the PL OA is reset to zero, and the contents of the OA register 6 are transferred to register 1 of the (i + 1) -th channel;

if the section of the channel and channel falls on the co. no part of the channel that operated in mode C, then the memory access is the same as the previous one, when restored, it is reset to the zero of the PA, the contents of the PA register 6 are transferred to the 1 (/ -f 1) -th channel and address X is transferred to the i-ro channel register.

In order to store addresses X, space can be allocated in ZU. In addition, if necessary, the parameters of the connected channels (addresses of the first, subsequently occupied cells) can also be placed in the memory for temporary storage.

The subject invention ji and

A store memory containing a drive connected to the Number register, the register of the current free cell Lam, connected to the register of the last occupied cell, control unit, block I, differing by the fact that in order to expand functional capabilities of the device, it contains the register of the first occupied memory cell, connected by means of two-way communication lines to the register of the current free cell, the block of AND circuits, and the register of the last occupied memory cell, and the mode register, input to orogo connected to blo, ky u.pravleni, and an output - to one .From input AND gates, and outputs the other input of which is connected to the accumulator and the register number.