SU980163A1 - Permanent storage - Google Patents

Description

The invention relates to computational techniques and can be used. It is called for building discrete information storage devices. There are memory storing devices consisting of an address decoder, the outputs of which through the first group of elements OR are connected to the inputs i of the accumulator, the second group OR, whose inputs are connected to the outputs of the accumulator, and the outputs through the reading amplifiers to the adder ij. But all these constant zapichinayusch devices have a large amount of equipment and low information capacity. The closest in technical essence to the proposed is a memory device consisting of a decoder, the outputs of which are connected to the inputs of the accumulator and the OR elements of the first group, the number register, the inputs of which through the elements OR of the second group are connected to the outputs of the group of the corresponding elements AND, the first inputs elements And connected to the outputs of the drive, and the second - with the outputs of OR the first group 2. The device has a large amount of equipment and, consequently, low reliability. So, for example, the number of elements And in a group is equal to, where N is the number of stored numbers in 1 pg; B is the number of groups into which the number is divided; n is the width of the initial numbers. And the number of elements OR of the second group is equal to n, with all the elements on the n inputs. The purpose of the invention is to increase the reliability of the device. The goal is achieved by the fact that a permanent storage device containing a decoder, the output of which is connected to the drive input and the input of the first block of OR elements, the second block of OR elements whose output is connected to the first input of the shift register of the number and the AND element, additionally contains a pulse generator, the output of which is connected to the first input of the element And, the second input of the element And is connected to the output of the shift register of the number, the output of the element And is connected to the third input of the shift register of the number, the fourth input to expensively connected to the output of the drive.

The drawing shows a storage device for storing four-digit numbers.

The device contains the decoder address 1, the first group of elements OR 2, the storage elements 3 ,, drive 4, the shift register 5 numbers, two-input elements OR b of the second group element And 7 and generator 8.

The output of address decoder 1 is connected to the inputs of the first block 2 OR elements and to the corresponding storage elements 3 of the accumulator 4. The output of one OR element of block 2 is connected to the input of the high bit of the shift register 5, the number of (n - 1) inputs of the high bit of register 5 is connected to the corresponding outputs of the block 6 elements OR The first inputs of the block 6 elements OR are connected to the outputs of the accumulator 4 and the second to the corresponding outputs of the block 2 elements OR.

The inverted output of the higher bit of register 5 is connected to the second input I 7, and the first input I 7 to the output of the generator 8. The output 7 is connected to the shift circuit of the register 5. The remaining inputs of the register 5 are connected to the outputs of the matrix drive 4. The outputs of the register 5 numbers are the output of a memory device.

The storage device operates as follows.

After the address code is decoded by the address decoder 1, a signal appears at one of its outputs, which is fed to one input of the block of the corresponding element OR 2 and to the input of the matrix accumulator 4, providing the reading of the required number from the storage elements 3 of the accumulator 4. Read number code from the accumulator 4 enters the register 5 numbers either through a block of 6 OR elements (part of the number bits), or a mine. Quantity dvuhkhodonN

All of the elements OR 6 are equal to -r - 1. Therefore, if the read code is stored in the leftmost memory, elements 3 of drive 4, then all bits of the number, except the youngest, go to register 5 through the elements OR b. At the same time, code 1 is recorded in the high register bit 5 by the same access signal, taken from the output of one of the OR 2 blocks, code 1. The signal from the inverse output of the high bit of register 5 closes AND 7 on one input, therefore, the signals from the output generator 8 does not enter the shift register circuit 5. The read code of the number

is in the upper bits of the 5 number register and can be issued from the memory;

When referring to the number stored in the rightmost memory

elements of the accumulator 4, the read n-bit code of the number is output to register 5, mine the block 6 elements OR, and the same signal is received from the output of the decoder 1 through

the corresponding element OR 2 goes to the second bypass of the corresponding OR 6, writing down the unit code in (n + 1) register bit 5, Since register 5 was canceled before being addressed, then the inverse output of the high bit and register 5 will be a single signal, which opens the second input. AND 7. The signals of the generator 8 through open AND 7 enter the shift circuit of register 5, providing a shift to the left until the unit code from (and + 1) bit of register 5 is copied to its most significant bit As a result, a zero code will be set on the inverse output. 7 and AND zakroets .Sdvig information is terminated, the code number again okazhets in older times rows (except the most significant bit) of the register is 5, and may be issued from the memory. In the proposed device, the amount of equipment is reduced by reducing the number of elements.

AND OR 6. In particular, one element is used in the arrangement jjBe.

And instead of t. n in the known and (n - 1)

double-tail or b instead of p on the inputs in the prototype. If the generator in the proposed device is replaced by three equivalent two-input elements AND, then the gain in AND and OR of the second group will be

. ()

N

+ 1

P

4 (p / -)

3 + n

N

where (n) .- number of elements

AND (OR) in the prototype, (n - 1) - the number of OR in

the proposed device 4. - total AND

(including generator)

5 in the proposed device.

In addition to Ioro, in the proposed device are significantly reduced, and switching links are reduced by 0 compared with the prototype.

In the accumulator 4 devices, all numbers N are divided into b groups by N / b, numbers in each group. Each group of numbers is stored in a string memorizing, x 5 elements 3 accumulator 4 compressed

Claims (1)

Claim Permanent storage device containing a decoder, the output of which is connected to the input of the drive and the input of the first block of OR elements, the second block of OR elements, the output of which is connected to the first input of the shift register of the number, 5 and the And element, characterized in that, in order to increase the reliability of the device, a pulse generator is inserted into it, the output of which is connected to the first input of the And element, the second input of the And element is connected to the output of the shift register of the number, the output of the And element is connected to the third input shifts the number register, the fourth input of which is under 15 keys to the output of the drive.