SU822292A1 - Fixed storage - Google Patents

Description

This invention relates to computation. technique, and can be used in memory devices of digital computers with sequential processing and formation. It is known a storage device (ROM) with input of information in a sequential code, which contains a register whose inputs are connected to corresponding logical buses, address buses, AND and OR elements, the first inputs of AND elements connected to the corresponding register outputs, the second to the corresponding address buses, and outputs - with the inputs of the element OR The disadvantage of this device is a large number of register bits when storing a large number of numbers, since a register is needed to store mn-bits m + n-1, where m is the number of numbers, n is the size of the recorded numbers .. The closest to the invention by technical essence is a port storage device, containing a shift register, elements AND by the number of bits of the shift register .and elements, and the outputs of the shift register are connected to the information inputs of the AND elements, the control input of which is connected to the corresponding address bus, and the output is connected to the input of the OR element, the inputs of the shift register are connected to the corresponding buses of logical zero and one, The corresponding input of the shift register is connected to the busbar. Circulation, and the output of the last bit of the shift register is connected to the input of its first bit 2j. The disadvantage of this ROM is its complexity when storing large arrays of numbers. The purpose of the invention is to increase the information capacity of the device. The goal is achieved by the fact that the device containing the first ring shift register, the inputs of which are connected to the logical zero and one buses, the clock bus, the reference bus and the installation bus, the OR element, the iifo Topop C9edine inputs (echoes and elements AND groups, address buses are entered shift register, trigger, AND element, the second ring shift register, two groups of OR elements, whose inputs are connected to the corresponding address buses. The outputs of the OR elements of the first group are connected to control The inputs of the elements AND of the group and the outputs of the elements OR of the second group are connected to the information inputs of the shift register, the information output of which is connected to the write enable input of the second ring of the shift register and the single trigger input, the zero input of which is connected to the setting bus of the initial state, output the trigger is connected to the first input of the element I, the second input of which is connected to the bus of clock pulses, and the output to the clock inputs of the second ring shift register, the setup inputs of which are connected to the installation inputs of the first ring shift register, the information inputs of the second ring shift register are connected to the information outputs of the first ring shift register, and the information outputs are connected to the information inputs of the AND group, bus Circulation and clock elements connected to the corresponding shift register inputs.

The proposed device makes it possible to reduce the number of memory cells of shift registers and elements in comparison with the known device with. storing the same number of numbers.

This is achieved due to the possibility of dividing the Euler graph into subgraphs with an equal number of edges, which is equivalent to representing an array of 2 n-bit numbers as n-bit groups with different number of ones and a different combination of ones and zeros in them. This allows the initial code of the number to be represented as several initial codes of numbers which are written accordingly in a ring shift register, from which these initial codes of numbers are read into another ring shift register, from which the necessary number is directly selected.

Figure 1 shows the block diagram of the device on 15 five-bit binary numbers; figure 2 - timing diagram of the device.

The diagram highlighted (figure 2) a- signal Circulation on the bus

Managing Appeal; b- signal on the selected address

tire; c - clock pulses "and clock

control bus; g, d. signals on the outputs of the register

shear;

 W- signal at the trigger output; and - the signals at the clock inputs of the second ring shift register;

K - signal on the installation bus

initial state; l- signals at the output of the device. The proposed ROM (Fig. 1) contains the first circular shift register 1, which is left of the memory cells, the second circular shift register 3, which consists of memory cells, AND 5 elements, OR 6 element, first group of OR 7 elements, address buses 8, the second group of elements OR 9, the shift register 10, consisting of cells 11, memory, trigger 12, AND element 13, control circuits 14, 15 clock, 16 reset, 17 and 18 logical 1 and O respectively.

Ring registers 1 and 3 of the shift are designed to record the initial codes of numbers determined by connecting the information parallel inputs of registers, and the inputs of the first ring register 1 of the shift are connected to buses 17 and 18 logical 1 and O, and the inputs of the second ring 6 of the shift register 3 - to information the outputs of the first ring register 1 shift, and form the drive information. By changing the connection of the information parallel inputs of the ring registers 1 and 3 of the shift, it is possible to change the written initial codes of numbers, thereby changing the array of numbers stored in the device.

The shift register 10 is designed to sample a certain starting code from the first ring shift register 1.

Two groups of elements OR 7 and 9 serve to organize a random sample of numbers from a device at a given address by connecting the inputs of these elements to the corresponding address buses 8, and to select one number to the selected address bus 8, you must connect one at a time. the input of the corresponding elements OR 7 and 9.

The number of numbers written to the device is n x p, where n and the number of cells 4 and 11 of memory in the second ring register 3 shift and the register 10 shift, and the size of the numbers written in the device is equal to the number of numbers written in the second ring register 3 shift-.

The proposed ROM works as follows.

Claims (2)

1. Authors certificate of the USSR -№ 491157, C. 11 C 17/00, 1975. 2. Authors certificate of the USSR 565326, C. 11 C 17/00, 1977 (prototype).