SU849303A1 - Fixed storage - Google Patents

Description

(54) PERMANENT STORAGE DEVICE

The invention relates to computing and can be used in memory devices for digital computers with sequential processing and formatting. A permanent memory device (ROM) with information in a sequential code is known that contains a register, the inputs of which are connected to the corresponding logical busses, and address buses, elements AND and OR, the first inputs of elements AND are connected to the corresponding outputs of the register, the second - with corresponding address buses, and outputs - with inputs of an IP element j The disadvantage of this device is a large number of register bits when storing a large number of numbers, since for storing n-digit numbers eobhodim register bit of clarity m-t-n-1, where m number of numbers, an- a width of Izapisannyh numbers. The closest in technical essence to the present invention is a device that contains a shift register, control buses, AND elements by the number of register bits and an OR element, and the outputs of the shift register bits are connected to the information inputs of the AND elements whose control inputs are connected to the corresponding address buses, and the outputs are connected to the outputs of the element OR, the information inputs of the shift register are connected to the corresponding buses of the logical zero and one, the enable input of the record of the shift register It is connected with the bus, and the output of the last bit of the shift register is connected to the input of its first bit. A disadvantage of the known ROM is its complexity in storing large arrays, numbers, since the number of storage cells m of the shift register is equal to the number of stored numbers in the ROM. The purpose of the invention is to simplify the device. The goal is achieved by the fact that a permanent storage device containing a shift register, informational inputs of which are connected to the corresponding buses of logical zero and one, and outputs - to informational inputs of the main elements AND, the outputs of which are connected to one input of the element OR, and the control bus , clock and setpoint bus to the initial state, to which the corresponding inputs of the shift register are connected, it contains additional elements AND, trigger, binary counter and groups of elements OR, They are connected to the address buses, the outputs of the OR elements of one group are connected to the corresponding control inputs of the main AND elements, and the outputs of the OR elements of the other group are connected to the corresponding control inputs of the additional AND elements, the information inputs of which are connected to the outputs of the register bits shift, and the outputs are connected to the corresponding inputs of the element OR the inputs of the binary counter are connected to the control buses. Circulation, clock, and to the reset bus to the initial state, which is connected to zero mu rhodu trigger output to zero torogo connected to the first control input capstan mu core element and a single output - to the first control input and additional elements, the trigger input of unit connected to the output of the binary counter. . FIG. 1 shows a block diagram of a device on 36 eight-bit binary numbers; in fig. 2 - oriented Euler graph for four-bit: binary numbers. ROM contains a circular shift register 1, consisting of memory memory cells 2, main AND 3 elements, additional AND 4 elements, the first group of 5 SHE 5 elements, the second n group of 6 elements, the OR 7 element, trig ger 8, binary counter 9, control buses: address 10, Address 11, clock 12, settings in the initial state 13, logical 1 and O, respectively 14 and 15. Forward and reverse outputs of the shift register 1, which are forward and 8 34 reverse outputs its cells 2 memory connected to the information inputs of the elements And 3 and groups of elements And 4, the second control inputs of which are connected to the outputs of the two element groups OR 5 or OR 6, respectively. The outputs of the elements And 3 and the group of elements And 4 are connected to the inputs of the element OR 7, and the first control inputs of the elements And 3 and the group of elements And 4 are connected respectively to the zero and single outputs of the trigger 8, the single input of which is connected to the output of the binary counter 9. Inputs two groups of elements OR 5 and OR 6 are connected to the corresponding address buses 10. Bus 11 Circulation is connected to the inputs of the write enable of the shift register 1 and the counter 9. The clock bus 12 is connected to the clock inputs of the memory 2 cells and the counter input of the counter 9. The installation inputs of the memory 2 and the counter 9, as well as the zero input of the trigger 8 are connected not to the 13 settings to the initial socket. Information parallel inputs of the shift register I are connected either to bus 14 of logical 1 or to bus 15 of logical O. Shift register 1 is designed to record the initial code of the number determined by connecting information parallel inputs of shift register 1 with these or other buses 14 and 15 of logical 1 and Oh, and is the storage of information. By changing the connections of the inputs of register 1 to the logical buses, the initial code is written to the shift register 1, and thereby the array of 2n-bit numbers written to the device is changed. In the new array, 2n-bit numbers consist of another set of n-bit numbers, which is determined by the new initial code written to shift register 1. Groups of elements OR 5 and ШШ 6 serve for organizing a random sample of numbers at a given address by connecting the inputs of these elements to the corresponding address buses 10, and for sampling one number to the selected address bus 1 О connect one input of the element OR 5 and one input of the element ШШ 6 The ROM works as follows. In the initial state, the shift register I, trigger 8, and counter 9 are in the zero state. At submission of the 1J operation. On the pulse, the enable signal arrives at the inputs of the shift register 1 and counter 9, which prepares the count input of counter 9 and. In shift register 1, it writes the initial code of the number, which from the outputs of the memory stack 2 goes to the information inputs of the corresponding elements 3 and 4. Simultaneously with the impulse circulation, one is excited per address bus 10, from which the enabling signal through one element OR 5 and one element ШШ 6 is supplied to the second control inputs of the corresponding elements I 3 and 4, and since the first control inputs of all elements 3 have the enable signal from the zero output trigger 8, then from the output of the element I 3 through the element Or 7 on stroke device receives the first bit of the selected number. After forming the output of the device of the first bit of the selected number, the first clock signal is sent to the bus 12, and the information is shifted, in the register of 1 shift by one bit around the ring, to the device output. The second digit is the initial code enters the prepared counting input of the counter 9. After forming the output of the device of the second bit of the selected number, the second clock signal is applied to the bus 12, and the information is again shifted in the shift register 1 by one bit around the ring, connected to the output ode of the device is the third digit of the initial code, and the clock signal also enters the counting input of the counter 9.. After performing n-1 shifts by applying n-1 clock pulses, where the n-bit of the numbers stored in register 1 of the shift, the first n bits of the selected number, which are bits of one of the n bit numbers written in shift register 1. When a clock pulse arrives, the information is shifted in the shift register I by one bit around the ring, and the output of the counter 9 terminates the formation of a signal that arrives at the unit 03 6 trigger input 8 and sets the enable signal at its unit output; cash that is fed to the first control inputs of all elements AND 4, thereby connecting to the output of the device the output of another cell 2 of the memory from which information flows through the elements AND 4 and OR 7 to the output of the device, and n + 1 bits of the selected the number which is also the first bit of the n-bit number recorded in the shift register I. With the arrival of subsequent n-1 clock pulses, the remaining n-1 bits of the second n-bit number recorded in shift register 1 are selected from the shift register 1, and the last n-1 bits of the selected number are formed at the device output. . Thus, after the completion of the 2n-1 clock pulse, all 2n bits of the number selected from the device are formed at the device output. Then, on the setting bus 13, a signal is generated in the initial state, at the end of which the excitation is removed from the address bus 10 and the bus 11 Reversal. In the shift register 1, the trigger 8 and the counter 9 are set to the zero state. The device is ready for the next call. In the proposed device (Fig. I), 36 eight-bit binary numbers are stored (6 36, the number of permutations with repetitions of six elements of 2). As the starting code of the number in register 1, code 100 is written, which is the code of an oriented cycle formed by an oriented Eulerian graph. For four-bit numbers, the oriented Euler graph (Fig. 2) has edges. Each edge of the graph is assigned one four-bit number. The sequence of non-repeating ribs is closed when from ocnefj, oBaTenbHoii bypassing in the direction of the trails form a cycle. To obtain an ode to an oriented cycle, you need to take the leading bits of the numbers, which correspond to the edges of the cycle when sequentially traversing the cycle in the direction of the tracks. Start bypassing Tsigapu Mozho from any edge belonging to this cycle.

The oriented cycle code 100 contains the numbers 1001, 0010 and 0100. From the oriented cycle code by the n-1 shift (where n is the digit number of the graph numbers) in the direction from the lower digits to the older ones (left), we get the number codes that correspond to this oriented code. cycle

one

001

010

100

As a result of the shifts in the columns, we get three numbers that correspond to the edges belonging to the given cycle {FIG. 2) Q

Since the 2 memory cells of the 1 shift register also have reverse outputs, in fact there are two initial codes written in register 1: 100 and 011, Code 011 also corresponds to a cycle in the Eulerian graph with edges, which correspond to ITO numbers, 1101 and 1011, for example

sh

BY

101

011

The device (Fig. 1) stores eight-digit numbers consisting of two four-digit numbers, which are recorded in register 1 and are selected from register 1 in sequence

According to the connection of information parallel inputs of register 1 to buses 14 and 15 of logical 1 and O, 1 is recorded in memory cell 2.1, and O is recorded in cell 2.2 and 2.3. Therefore, when the first number is read out, the numbers 1001 and 0110 are formed at the outputs of memory 2.1. , at the outputs of cells 2.2-0010 and 1101, and at the outputs of cell 2.3 - 0100 and 1011.

When reading the second number from register 1, the numbers 1001 and 0110 are formed at the outputs of memory cell 2.3, the numbers: 0010 and 1101 - at the outputs of memory cell 2.1, and the numbers 0100 and 1011 - at the outputs of memory cell 2.2 This is because The end of the first number in register 1 is set to code 100, which is shifted by one bit along the ring n by a clock pulse. In shift register 1, code 001 is set, which is the initial

code when sampling the second four-digit number. Upon receipt of the subsequent n-1 clock pulses, the following numbers will be generated on the direct outputs of register 1:

SOG

010 100 .001

The following numbers are formed on the reverse outputs of the memory cells 2

Gsh

101.

01 1 110

Thus, when reading the first and second numbers from the same

the same 2 memory cells of register 1 read different numbers, since a shift occurs in the initial code relative to the outputs of register 1 when the second number is read relative to

5 first. In the above example, this shift occurs left-to one bit of register 1, since n-m, where the size recorded in the register of 1 numbers is 4, am is the number of bits in register 1, is 3.

In the general case, if, then along the ring, the shift of the initial code occurs to the left by bits of the register 1. If, then the shift along the ring occurs to the right by bits

register 1. If, then. and shear ring neg, i.e. from the same. The 2 register memory cells 1 match the same numbers.

0 If the number 10010010 is selected at the address at which one of the address buses U is excited, then the address bus is connected to this address bus by one input of the elements OR 5. -1 and OR b. one

5 (Fig. 1).

To select the number 01100100, the corresponding address bus 10 is connected to this bus by one input of the elements OR 5.2 and ШШ 6.3 (Fig. 1).

0 For sampling the number 11010110 over the corresponding address bus 10, this bus is connected to one input of the elements OR 5.4 and OR 6.6 (FIG. 1). In some cases, information

Claims (2)

5 are represented as multiple oriented cycle codes. Then shift register 1 consists of several independent shift registers. If the proposed device stores large-size numbers, then these numbers are formed from more than two n-bit numbers recorded in shift register 1. For this purpose, more than one group of AND elements, the corresponding number of OR elements, the trigger and the connection between them are additionally introduced into the device. In the proposed device, which contains the current shift register 1 with 2 second cells, it stores (2m) 2n bit cells (the number of permutations with repetitions of 2gp elements of two each). To store this amount of information, the required number of elements (excluding the counter and the trigger is 4t + 4t + I Sm + i. WHERE 4ifn is the number of elements OR 5 and OR 6; 4t is the number of elements AND 3 and AND 4; 1 is the element OR 7. The total number of inputs for these elements is 2 (t) + 34t + 4t 8t 16t. In the known device, (2t) memory cells are required for storing this amount of information, and the required number of elements is (2g) +1 1, ( 3) where (2iTi) is the number of elements AND; 1 is the OR circuit. The total number of inputs for these elements is equal to. 2 (2t) × (2t) 12t (4) Comparing formulas (l) and ( 3), (2) and (4) it can be seen that the proposed device gives a gain both in the number of elements and in the number of inputs for these elements, and the gain in elements is obtained already at, and by the inputs at. As can be seen from a comparison of the known The device with the proposed device has a gain in the amount of equipment, and the largest gain is received in the number of memory elements, since only m memory elements are required for storing 84 3 (2t) K 2n bits. . DETAILED DESCRIPTION OF THE INVENTION A permanent memory device containing a shift register, the information inputs of which are connected to the corresponding busses of logical zero and one, and the outputs - to information inputs of the main elements, the outputs of which are connected to one input of the OR element, and the Turn control bus, clock and bus of the installation to the initial state, to which the inputs of the shift register are connected, characterized in that, in order to simplify the device, it contains additional elements AND, trigger, binary account The sensor and groups of OR elements whose inputs are connected to the address buses, the outputs of the OR elements of the same group are connected to the corresponding control inputs of the main AND elements, and the outputs of the OR elements of another group are connected to the corresponding control inputs of the additional AND elements, the information inputs of which are connected to the outputs of the bits of the shift register, and the outputs are connected to the corresponding inputs of the OR element, the inputs of the binary counter are connected to the control buses, and the tachometer and the plant bus are initially The state that is connected to the zero input of the trigger, the zero output of which is connected to the first control input of the main elements AND, and the single output to the first control input of the additional elements AND, the single input of the trigger is connected to the output of the binary counter. Sources of information taken into account in the examination 1. The author's certificate of the USSR No. 491157, cl. G 11 C 17/00, 05.11.75. 2. USSR author's certificate number 565326, cl. G II C 17/00, 07.15.77 (prototype). W SC1 0000 nil ag.g