SU1725215A1 - Device for sorting numbers - Google Patents

Abstract

This invention relates to automation and computing. The purpose of the invention is to increase speed. The device contains a minimum number allocation unit (BVMCH) 1, a sorted number exclusion register (RIOS) 2, blocks for determining the number of ones in the binary code (ROOM) 3, 4, a memory block (BP) 5, output registers 6 sorted numbers, OR elements 7. Among the original numbers, BVMCH 1 defines and marks the minimum number (s). WELLS 4 and 3 determine, respectively, how many minimum numbers allocated BVMCH - Ci and how many of them have already been sorted (how many units are written in RIOS 2) - Ci. The received codes are sent to the address inputs of BP 5, which forms a Window-type mask containing units in the remaining bits. The allocated minimum number is written to the marked output registers 6. Tab. 1, 2 Il. Yo

Description

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The invention relates to computing and can be used in database machines and information retrieval systems.

Devices for sorting numbers are known that contain descramblers, groups of OR elements, analysis nodes and encoders. The operation of these devices is based on the algorithm of sequential reduction of the set of sorted numbers by excluding the smallest number from each successive step,

A disadvantage of devices is their unsuitability for sorting large numbers. This disadvantage is due to the use in the devices of the principle of double conversion of codes of numbers — positional to distribution, and distributional - into positional. As the size of the sorted numbers increases, the hardware costs for decoding the encryption of their codes sharply increase, which makes it difficult to implement devices in practice.

It is also known to have a device for sorting numbers containing pulse shapers, a group of OR elements, an exclusion register of sorted numbers, and a unit for determining the number of ones.

The disadvantage of the device is its low speed, due to the cost of several cycles for the allocation and issuance of each sorted number.

The closest in technical essence to the present invention is a device for sorting n numbers, containing the smallest number allocation unit, n input adders, output adder, sorted number exclusion register, unit for determining the number of ones, counter, impulse drivers, and AND, and NOT elements group of elements OR.

A disadvantage of the known device is its low speed, due to the separation in time of the process of alternately allocating the smallest numbers and the process of forming the resulting array. The processing of the initial disordered array containing among its elements H pairwise different numbers is performed (by the device) in (H + n) cycles, of which H cycles are spent on their own sorting, and n cycles - on the formation and elementwise output of the resulting array.

The purpose of the invention is to increase the speed of the device by combining in time the processes of extracting the smallest numbers and forming an ordered array of them.

The goal is achieved by the fact that in a device for sorting numbers, containing a minimum number allocation unit, an exception number register, a first unit

determine the number of units and the group of elements OR, and the inputs of the 1st number of the device (i 1, 2п; n is the number of sorted

numbers) are connected respectively to the information inputs of the i-th group of the minimum number allocation unit, the direct outputs of the number exclusion register — to the inputs of the first unit for determining the number of units; the second unit for determining the number of units, the memory unit, and

n output registers, the inverse output of the 1st bit of the number exclusion register being connected to the ith permitting input of the minimum number allocation unit, the 1st address output of which is connected

with the input of the i-ro setting of the number exclusion register in the single state, the i-th input of the second unit for determining the number of units and the first input of the 1st element of the OR group, the second input of which is connected to the direct output of the 1st discharge register register numbers, the installation input in the zero state of which is the input of the initial installation of the device, the information outputs of the minimum number allocation unit are connected to the information inputs of all output registers, the outputs of the first and second units of determining the number of units are addressable memory block inputs, i-th output

which is connected to the recording resolution input of the 1st output register, the bit outputs of which are information outputs of the i-th group of the device, the clock input of the device is connected to the clock inputs of all registers, the outputs of all OR elements of the group are combined by assembly AND and are the end of work output devices.

Figure 1 presents the scheme of the device; Fig. 2 shows a variant of the minimum number allocation unit.

The device contains (Fig. 1) a minimum number allocation unit 1, a register 2 excluding sorted numbers, the first 3

and the second 4 blocks for determining the number of units in binary code, block 5 of memory, n output registers 6 sorted numbers (n is the size of the processed numeric arrays), a group of n two-input elements OR 7,

informational inputs of the sorted numbers Ai, A2, ..., Ap, input LU of the initial installation of the device, informational outputs of the sorted numbers Bi 62 ....- ЈVp, exit and termination of the device operation.

The minimum number allocation unit 1 (Fig. 2) contains a rectangular matrix of n x k analysis cells, where k is the size of the sorted numbers. Each cell 1c, where i 17n, I 1, k, has a resolution input Rc, an output resolution Pn, an information input ai, and an information output. The analysis cells, forming a separate row matrix, are connected in series along the resolution inputs and outputs. The resolution inputs of the H 1.12 i, ..., ln 1 cells of the first column are the enable inputs of block 1. The resolution outputs of the Hie cells. The l2kIn k of the last column are the address outputs of block 1. The information inputs of the cells of the 1st row form the information inputs of the sorted number At - anai2 ... aik. The information outputs of the cells are combined in columns and form the information outputs bi, D2, ..., bk of block 1.

The analysis cell consists of a repeater 8, an equivalence element 9, and an implication element 10.

Elements 7-10 are performed according to a scheme that provides the implementation of the INSTALLATION function at the connection points of the outputs.

The device is based on the algorithm of sequential reduction of the set of sorted numbers. The algorithm includes H steps, where H is the number of pairwise different numbers in the source array. At the same time, at each hth step, the group of C (s) identical smallest numbers is excluded from the current set of yet not sorted numbers.

The device works as follows.

Sorted numbers that form a disordered array are fed through the inputs Ai, A2, ..., An of the device to block 1 for the selection of the minimum number. At the same time, the initial setup signal is applied to the input of the NU device, which asynchronously resets all bits of the register 2 is performed. From the inverse outputs of register 2, the corresponding inputs of block 1 receive single signals Pi, P2, ... Pn. resolving the analysis in block 1 of all n sorted numbers.

In block 1, among the numbers Ai, A2An, the minimum number B (1) min (Ai, A2, ..., An) is found. The code of this number is transmitted from the information outputs of block 1 to the information inputs of all registers 6. At the address outputs of block 1, a set of signals vi, V2vn is formed, in which the single values indicate the positions of the selected number B {1) in the source array.

The generated signal set vi, V2, ..., vn is fed to the inputs of the installation in 1 bits of register 2 and to the inputs of block 4.

Block 4 determines the number of single signals in the set vi, V2vn. The code C (1) ci C2 ... c q obtained at the outputs of block 4, where q log2 (n + 1), shows how many smallest numbers equal to B (1) are contained in the original array. At one time, the block 3 calculates the number of units in the bits of register 2. Code C (1) ciC2 ... Cq 0; formed at the outputs of block 3, shows how many numbers of the original array have already been sampled.

Codes C (1) and C (1) from the outputs of blocks 4 and 3 are fed to the address inputs of memory block 5. Block 5 forms a n-bit window type mask containing a series of C (1) units in bits from (C (1) +1) through (C (i) + C (ijth and zeros in the rest bit dah

Block 5 can be made in the form of a ROM with a capacity of 4 × n-bit words. An example of firmware ROM for the case n 4 is given

5 in the table. ROM cells whose addresses are not listed in the table may contain arbitrary information.

From the outputs of block 5, the bits of the mask that have been formed go to the inputs of register register 6 resolution. At the same time, the i-th mask mask is input to the register recording resolution b | and allows or denies the reception of information this register from the information outputs of block 1.

5 According to the next sync pulse (the synchronization circuits in Fig. 1 are not shown), the code of the smallest number B (1) allocated by block 1 is received in registers 61-6cV unlocked by the record ones

0 bit masks. The contents of the remaining registers 6ci + i. 6n does not change. Simultaneously by a set of signals vi, vavn,

incoming from address outputs of block 1, are set to 1 bits of register 2, corresponding to the positions of the selected number B (1) in the source array. Thus, these numbers are excluded from further consideration in block 1, since the number of zero signals per allowing

five

0

the inputs of Pi, P2Pn block 1 increases by

value). As a result, the current set of sorts being sorted is reduced by eliminating from it C (1) the same smallest numbers.

5 in the next cycle, the operation of the device is repeated in a similar manner. In this case, at the outputs of blocks 4 and 3,

CODES WITH (2) AND WITH (2) WITH (1) + C (1) WITH (1)

accordingly, and at the outputs of block 5, a mask is formed with a window with a width of C (2) bits and a left border equal to C (2) +1. In this case, the next number B (a) B (1), allocated by block 1, is accepted into registers +1 - 6c i + C2 - and in register 2 is additionally set to the C (2) unit state of the bits corresponding to the positions of the number B (2) in the source array.

Thus, in each hth operation cycle of the device, the current set of sorted numbers is reduced by excluding from it C (h) the same smallest numbers, and the current set of already sorted numbers is supplemented by these numbers. The window formed by block 5 shifts from beat to beat to the right. The single signals taken from the direct outputs of register 2 mark the positions of the already sorted numbers, and the single signals at the inverse outputs of register 2 mark the positions of the numbers that have not yet been sorted in the original array. The HF 82 ... Sun (n) numbers sorted by the end of the h-th cycle are in the registers 6i-poor.

The sorting of the initial array ends in the Nth bar, where НЈ {1, 2, ..., n} is the number of pairwise different numbers among Ai, A2, ..., AP. In this cycle, the values of C (n) and C (n) are formed at the outputs of blocks 4 and 3, and C (n) + C (n) n. Simultaneously, at the outputs of all OR 1 - In elements, single signals appear, which leads to the development of a single sign a, indicating the end of the sorting process. By the end of the Nth clock, at the next sync pulse, the last of the H numbers allocated by block 1 is accepted into registers 6on + 1-6P. In the next clock cycle, the next array of sorted numbers can be fed to the inputs Ai, A2, ...-, An of the device.

The minimum number allocation unit 1 operates as follows.

To horizontal rows of analysis cells

111 - Hk, l2T l2kIn1 - Ink SUBJECT BINARY codes of the sorted numbers Ai, A2, ..., An so that ai corresponds to the highest, aik - the youngest bit of the 1st. Of all the n input codes, only those for which the logical inputs 1 are present on the enable inputs of block 1 are analyzed.

In block 1, an algorithm for indating a comparison of numbers was used.

If the number Ai is not involved in the comparison, then the resolving input Pi of block 1 contains a logical O signal. This signal propagates through repeaters 8 of all the i-th row analysis cells and appears at the output of block 1 as a zero exclusion signal vj. In each cell of the i-th analysis

the zero resolution signal Rn is fed to the second input of the implication element 10, creating conditions for the appearance of the logical signal at the output of this element of the signal

1 (0 only with au 0 and Pc 1). Thus, excluding the number A) from the analysis in block 1 is equivalent to replacing it with a maximum number containing units in all bits.

0 If at least one of the numbers involved in the comparison contains O in the higher order, then this O is transmitted to the output of the implication element 10 and appears at the information output bi of block 1, because the outputs of all elements 10 of the first column are connected according to the INSTALLATION AND ,

If the AI number involved in the comparison contains a one in the higher order (au, 1), and the output L of block 1 is formed

If 0 is a logical O (bi 0) signal, this means that AI is not the minimum among the analyzed numbers. In such a case, at the output of the cell equivalence element 9, a logical signal appears

5 O (an ® bi)) 0), which propagates through repeaters of 8 cells z - hk and appears at the i-th address output of block 1 as a zero signal VL The appearance of a logical O signal at the inputs of the cell resolution Ii2 - lik creates the conditions for obtaining at the outputs of elements 10 the implication of these cells of the signals of logical 1. Thus, the number of AGs is excluded from further analysis by the least significant numbers.

If all the numbers involved in the comparison contain a one in the higher order, then the information output bi of block 1 is a logical 1 signal. In this case, the comparison of numbers continues on the least significant bits. In this case, in cells h2 - hk, I22 - 2k, ... In2 - Ink analysis, processes similar to those considered take place.

5 Thus, the selection of the minimum number by block 1 occurs as a result of the propagation of signals along the rows of analysis cells from left to right. The values of the digits of the allocated number appear

0 on informational outputs bi, b2bk

block 1, and the positions of the selected number occupied by it in the source array are marked by logical 1 signals at the corresponding address outputs vi, V2vn of block 1.

5 The device (4) for sorting numbers is chosen as the base object - the prototype of the claimed invention.

A significant technical advantage of the claimed device over the basic object is a higher

fast speed This advantage is achieved by the exclusion from the initial array of a group of identical smallest numbers at each sorting step. Indeed, the sorting of the original array containing H pairwise distinct numbers is performed by the base object in (H + n) cycles. The device performs the sorting of the same array by the N clock cycles, providing an increase in speed by (H + n) / H (1 + n / H) times. The maximum gain in speed (n + 1) is reached in the case when the initial array consists of n identical numbers. In this case, the sorting of the array by the base object takes (n + 1) clocks, and the device being inserted takes the I clock. The minimum gain (2 times) occurs when the source array does not contain the same numbers. In this case, the sorting of the array by the base object requires 2 steps, and the device claimed requires n steps.

Comparison of the base object and the claimed device by the duration of the operation cycle shows the following.

The duration of the operation cycle of the base object is

Tg T5 + T1 + + T15 + T16, (1)

where T5 is the response time of the minimum number allocation unit;

t is the time of summation of two c-bit codes on the adder;

TIO - time of receiving information in the register;

T15 is the response time of the unit for determining the number of units;

t TB is the time of receiving information in the counter.

For the device being claimed, the duration of the work cycle is determined by the expression

Tz T1. + GZ + G5 + TB,

where n is the response time of the minimum number allocation unit 1;

T3 is the response time of unit 3 for determining the number of units;

T5 is the response time of the memory unit 5;

Those - the time of receiving information in the registers 6.

From expressions (1) and (2) it follows that the ratio

Tj-Tz ti,

showing that the duration of the operation cycle of the base object exceeds the duration of the operation cycle of the claimed device

at least the time r is the sum of two k-bits.

Thus, the proposed device differs from the base object at a minimum of half as many clocks needed to sort the source array, and a shorter duration of each clock. As a result, the claimed device has at least twice as much

10 high speed.

If it is necessary to issue sorted numbers one by one, the claimed device can be used together with any known device.

15 parallel-sequential buffering. In this case, exactly n clocks will be spent on sorting each array, i.e. H steps less than in the base object.

20

Claims (1)

Claims An apparatus for sorting numbers, comprising a minimum number allocation unit, an exception number register, the first 25 unit for determining the number of units and the group of elements OR, and the inputs of the 1st number devices 0 1,2, p, p - number numbers to be sorted) are connected respectively to the informational inputs of the i-th The 30 groups of the minimum number allocation unit, the direct outputs of the bits, the number exclusion register are connected to the inputs of the first unit for determining the number of units, characterized in that 35, a second unit for determining the number of units, a memory unit and n input registers are entered into it, the inverse output of the 1st bit of the number exclusion register being connected to the i-th 40 by the enabling input of the minimum number allocation unit, the i-th address output of which is connected to the installation input of the 1st bit of the number exclusion register in the unit state, the i-th input of the second 45 of the unit for determining the number of units and the first input of the 1st element of the OR group, the second input of which is connected to the forward output of the 1st bit of the number exclusion register, the input of the setting to zero 50, the state of which is the input of the initial installation of the device, the information outputs of the minimum number allocation unit are connected to the information inputs of all output 55 registers, the outputs of the first and second units of determining the number of units are connected to the address inputs of the memory block, the i-th output of which is connected to the write enable input of the i-ro output register, the bits of which are information outputs of the i-th group of the device, clock the device input is connected to the clock inputs of all registers, the outputs of all the elements of the OR group are combined with the AND assembly and are the output of the end of the device operation. I - , gf four // I ii  . V. t p-c &