SU1441484A1 - Apparatus for associative coding and compression of volume of information - Google Patents

Abstract

This invention relates to automation and computing. Its use in multi-sensor experiments in nuclear physics makes it possible to increase the speed of action. The device contains a memory block 1, selectors 2, 3 codes, a counter 5, a pulse shaper 6, encoders 8-10, a trigger 11, a control block 1 2, and an And 1.5 element. By introducing a code selector, pulse generator 7, code conversion block 13, key block 14, and delay elements 16, 17, the device performs more complete information compression, which ensures more speed. 6 hp ff, 9 ill.

Description

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The invention relates to automation and computing and can be used in information processing systems obtained in multi-sensor experiments.

The purpose of the invention is to increase the 6f, icT roaming device.

Figure 1 shows the functional diagram of the device; 2 shows a memory block; in FIG. 3, the first code selector; FIG. 4 shows the second code selector; in FIG. 5, the third code selector; in fig, b - the first pulse shaper; in Fig.7, the second driver 1-Mpulsov; 8 shows a control unit; figure 9 shows a code conversion unit

The device contains blbk 1 memory first 2, second 3 and third 4 code selectors, counter 5, first 6 and second 7 pulse shapers, first 8, second 9 and third 10 encoders, trigger 11, control unit 12, conversion unit 13 codes, block 14 ktgochey, the element And 5, the first 16 and second 17 delay elements, the input 18 of the beginning of the cycle, the input 19 of the end of the cycle, the input 20 of the reset,; act input 21 j, information outputs 22, first 23, second 24, and third 25 control outputs.

The memory unit 1 comprises a storage module 26, a first 27 and a second 28 groups of keys, a decoder 29, a switch 30, a first 3J and a second. 32 one-shot, element RSH 33, delay element 34, first 35, second 36 and third 37, fourth input 33, first 39, second 40 and third 41 outputs.

The first selector 2 of the code contains the triggers 42 groups of 43 elements NOT, the first - groups 44 - 48 elements I ;, the first 49 and the second 50 groups of elements OR, the resistor 51, the source 52 of constant voltage, the first inputs 53, the second - the fourth entrances 54 - 56, first exits 57, second exit 58, third exits 59, fourth 60 and five 61 exits, I

The second selector 3 of the code contains the triggers 62, the first - the fourth groups 63 - 66 elements AND, the group 67 elements OR, the group 68 elements NOT, the first 69 and the second 70 resistors, the source 71 of a constant voltage,

nepBfiie notes 72, the second - the fourth inputs 73 - 75, the first outputs 76, the second 77 and the third 78 outputs.

Treggy selector 4 code contains a one-shot 79, the element is NOT 80, the trigger 81, the first 82 and the second 83 elements OR, the first - the fourth elements And 84 - 87, the highlighter 88 positive differential, the first - the fourth drivers 89 - 92 delayed pulses, the first inputs 93, the second - the seventh entrances 94 - 99 ;, the first - the fifth exits 100 - 104,

The first driver 6 pulses contains the element And 105, one-shot 106, the element 107 delay, the first 108 and the second 109 inputs, the first - the third outputs 11 O - 1i 2.

The second pulse shaper 7 contains the element AND PZ, the element IPI 114, the first 115 and in the lib lib delay elements, the first retney inputs 117-1 19 and output 120.

The control unit 12 contains the first - third triggers-12 - 123, the first t 24 and the second 125 formulated delayed pulses, the first 126 to the second 127 elements OR, the left 128 and the second 129 elevens And, the first to the seventh inputs 130 - 136 $ per1; th - seventh outs 37 - 143.

The code conversion unit 13 contains a group of 144 elements i-lTlH, element AND 145, the first - fourth adders 146 - 149, the first; 150 and the second 151 groups of elements I., the first 152 and the second 153 registers, nefvye - the third outputs 160-162.

The memory module 26 may be executed on any of the memory elements of the conditionally constituting cube of memory containing matrices consisting of rows. The first and second modules of the module 26 are the address inputs of the rows of the matrices, respectively. The tert5-ha input is the input for reading the elements of the preliminary indication of the information contained in each module row 26. The first and BTOpije outputs of module 26 correspond to the outputs of the row and the output of the M matrix.

Groups 43 and 68 of the elements NOT and group 66 of the elements AND (FIG. 3 and FIG. 4) whose outputs through the corresponding resistors 51;. 69 and 70 are connected to the sources 52 and 71 of the constant voltage, function F-1 OR.

(diopiG rachor 79 (ifinr.5) can be performed on E.eeme Ge or 163, delay element 164 and trigger 165,

The device works as follows.

With the arrival of a 1-digit start pulse at input 18 (input 131 of block 12), a single output of flip-flop 121 (output 1LZ of G2) is applied to block 1D to interrupt the reading of words to an external recording device. The same potential through the OR elements 126 and I 128 sets in one state the trigger 122, which allows (blocking) the launching of the MEAF in the potential taken from its direct output (output 137 of the unit 12 - the output of the 2D device) recording its information on the outputs 22 into the memory elements of the module 26, and the input 20 of the device (input 133 of the block 12) is sent to the signal triggering the driver 124 and resetting the trigger 122, which prohibits further launches of the MESF in the output of information from memory block 1, through time the delay of the generator 124, equal to the termination of non-stationary processes in the MNAF, is given a reset signal to the initial state of the selectors and the counter 5 and to the input 119 of the generator 7, the output of which receives the unit write signal to the trigger 11 and the counter 5 providing the decoder 29 and keys 28 is selected for outputting the data of the first matrix of module 26 in the memory block. At the same time, this signal from the output of the imaging unit 7 is fed to the input of the delay element 16, which forms a delayed start pulse to the input of the one-shot 31 for reading data from the elements of the preliminary indication of the information availability of the first matrix of the module 26 to the inputs of the trigger 42 of the selector 2. At that ( due to the constant presence at the output of the one-shot 106 shaper 6 of a high potential), in the selector 3, the first bit from the low-order digits is automatically divided with a significant in1} law. The potential from the output of this bit immediately goes to the inputs 35 of the block for reading the data of the selected line and to the inputs of the encoder 9. From the outputs of the encoder 9, on the leading edge of the signal, through eleaN / 4

ment OR 33 starts the one-shot 32 and opens the corresponding key 27 through the delay element 34, thereby starting to read the selected line data to the selector 2, In the selector 2, due to the constant presence at the output 100 of the selector 4 (output of the one-shot 79)

10, the signals are automatically allocated from bits that contain the extreme units of the first one from the side of the Minimal bits of the cluster recorded in the selector 2.

15 As a result, the potential from the AJ output of the outputs 57 in the selector 2, corresponding to the youngest unit of the cluster, goes to the corresponding input of the encoder 8, and the discharge of R:

20 outputs 59, corresponding to the bit containing the highest cluster unit, to the input of the encoder 10,

To obtain a value corresponding to the number of neighboring units in the class, numerically equal to the difference B - A |, the outputs of the encoder 10 are connected to the inputs of the decremented adder 146, block 13, and the outputs of the encoder 8 - to the inputs of the readable same adder 146,

To obtain values corresponding to the coordinates of the midpoints of the clusters,

. Bj - Af numerically equal to AJ +, outputs

35 encoder 8 through a group of 144 elements OR are connected to the inputs of the first term of the adder 149 of block 13, to the inputs of the second term of which are shifted by one bit in the direction

The 40 least significant bits are connected to the outputs of the adder 146, which, for the cases of combining the number of adjacent units of dismembered clusters without shifting, are also connected to the input of the first second second cyMNtaTOpa 148, which duplicates the contents of the adder 146 in the absence of data at the inputs of the second term,

Thus, as a result of the above operations, the word consisting of matrix numbers, rows, coordinates of the middle of the cluster and the number of neighboring units in the cluster, respectively contained at the outputs of counter 5, adders 147, 149 and 148, was prepared for output. the readiness of this word to the conclusion is formed by the chain: encoder 10,

5l-i

the element OR 82 selector 3, the highlighter 88 positive differential, ele

cops AND 87 and OR 83 are the S input of trigger 123 of block 12.

With the establishment of the trigger .123, the AND 129 element is unblocked, transmitting the next clock pulse from the input 136 of the block 12 (device input 21) to the gate (reading) input of the selector 2 to read the prepared word to the external recording device, and to the input of the imager 125 , the output of which is connected to the reset inputs of the flip-flops 11 and 81 in the selector 4 and the input of the OR element. 127 of the block 12, from the output 139 of which it is fed to the input 55 of the selector 2 to reset the bits of the output cluster, the R input of the trigger 123 and the input 97 start the input one-shot 79 (inputs of the OR element 163 and the delay element 164) of the selector 4.

As a result, the work of the element And 129 is blocked and the data of the removed cluster is reset, and with the end of the operation of the single-selector 79, the data of the next cluster is selected in the selector 2 If the unit of this cluster is not contained in the last thirty-second bit of the selector 2 then the output of its data will occur in the order described above. Further, if this cluster in the selector 2 is the last one, then after it is reset, it is cleared from the information, and the output from circuit 58 unlocks element 105 of the former 6, which passes the signal from the output of delay 07 to the selective reset the input 74 of the selector 3 and the launch input of the one-shot 106.

As a result, a reset is made into the bit of the selector 3 corresponding to the line whose data output is completed, and the next line (bit) is selected with meaningful information and its data is read to the selector 2 in the order described above.

However, with the distribution of cluster units on the border of two adjacent rows, the order of operation of the device will change somewhat. The first signs of the distribution of units on the border of two adjacent rows are simultaneously

5 0 0 5

0

five

five

846

The presence of signals at the output 78 of the selector 3 and at the 15th output 60 of the selector 2. This opens the element AND 84 in the selector 4 and sets in one state a trigger 81, the potential of the zero output of which blocks element And 87, and the signal from the single output prepares And 85 and 86 elements are released. And block 13 of block 13, which controls the subtraction of a unit from adder 147, is released. Simultaneously with setting trigger one to one state, driver 89 is started, which generates a strobe signal to the inputs of groups 150 and 151 elements AND block 13 for rewriting the data of the first half of the cluster from the outputs of adders 149 and 146 to registers 153 and 152. Then, the signal through the delay of the generator 90 necessary for rewriting through the OR element 127 of block 12 is fed to the R input of the trigger 123, the one-shot input 79 and input 55 of the selector 2,

As a result, in selector 2, bits that contain the first part of adjacent cluster units are dropped into O, and in selector 3, through the delay of element 107, a neighboring bit with information is allocated and read from the corresponding data line in module 26 to selector 2 in the above described order-.

In this case, if the cluster actually turned out to be dismembered, then a high potential appears at the output 61 of the selector 2 and the And 86 element is deblocked, and the element 80 is blocked through the element 80. And 85 in the selector 4.

As a result, the readiness signal of a number, produced in the order described above by the selector 88, through the element 86, the driver 92 and the element ILE 83 sets the trigger 123 in block 12 to one state.

In this case, the output of the encoder 8 will be number A-; A.jj Oh, and therefore, at the inputs of the first term of the adder 149 in block 13 there will be a value recorded in the resistor 153. At the input and output of the adder 146 there will be a value B B, equal to the bit number occupied by the highest cluster unit numerically equal to the number of neighboring in the second half of the cluster, therefore, at the inputs of the first term of the adder 1-8 there will be a value equal to BK, at the inputs of its second term it will be the value of the previous difference B - A | recorded in register 152 and numerically equal to the number of neighboring units in first half of the day as well, and the output of the adder is 1L8

their sum is equal to

“F + B,

Since at the input of the second term of the adder 149 there will be a value of Vc / 2, then at the outputs of the adders 149 and 148 the resulting values will be obtained:

-. VC

J

 . -and

By - A; + B

to

numerically equal to the coordinate of the midpoint of a partitioned cluster and the number of units adjacent to it (outputs 161 and 160 of block 13).

However, depending on the number of neighboring units and their distribution on the border of adjacent lines, the number of the registered line will require correction, since the coordinate of the cluster midpoint may belong either to the previous line or the newly read line, In the second case, the result will correspond to the real one, and in the first case from line numbers must be subtracted by one. To subtract the units in these cases, the inverse transfer output of the adder 149 through the AND element 145, which is controlled by the potential from the direct output of the trigger 81 of the selector 4, is connected to the input of the subtracting unit in the adder 147. As a result, on. the outputs 160 - 162 of block 13 will always receive a result corresponding to the real values of the line numbers, coordinates of the clusters and the number of neighboring units in them. If there is no second half of the cluster in the next line

the number of neighboring units in them, regardless of their number and distribution at the boundaries of two adjacent lines, the data of undifferentiated cluster 45 are output for one touch, and divided into two cycles, the device reduced the average number of cycles needed to search for one significant bits of information from 1.55 to O, 66,

trigger, 42 selectors 2 will be at zero- 50 At almost all

0

five

0

The first in order cluster is selected, the units of which are not to be merged, therefore the impulse to be generated along the circuit: encoder 10, element OR 82, extractor 88, through element 85 and element OR 163 is fed to a reset in 0 of the one-shot trigger 165 79, which removes the output signals from the selector 2 in this state without destroying the information in it at the time of data output from the register .152, and then through the AND 15 element and the OR 83 element to the trigger state 123.

The output of the word recorded in the registers 152 and 153 of block 13 occurs in the order described above and then reset them in O with a signal supplied from the output of the driver) 25 blocks. 12, The same signal through the element OR 127 each time enters the reset in

the initial state of trigger J23 and the input 55 of the selector 2 for resetting the output data and finding new ones. Wrapped the output of the event data from module 26, reaching the final matrix set by switch 30, the output of which is after 0 elements OR 126 and 128 is sent to the S input of trigger 122, which allows the registration of data of the next event to the memory elements of the module 26. Periodic start-ups and shutdowns of the device from the registration and output mode can be performed by signals to inputs 18 and 19 (inputs 131 and 132 of block 12).

Thus, due to the derivation of the coordinates of the midpoints of the clusters and

the number of neighboring units in them, regardless of their number and distribution at the boundaries of two adjacent lines, the data of the undifferentiated cluster: 5 ditch are output per one contact, and the divided ones - in two cycles, the device reduced the average number of cycles required for searching. meaningful bit of information, from 1.55 to 0, 66,

0 However, almost all

data in which the data of the first half of the cluster recorded in the register 152 of block 13 are subject to output to the external device. In such cases, the potential element 86 from the selector 4 will block the AND element through the NOT 80 element. 85, However, in selector 2 there will be

abilities of neighboring units and the conditions of their distribution, data on clusters are output in the form of one word, which results in a further compression of the “information by volume,

I

The use of the proposed device leads to the elimination of the need for coding programs.

about clusters in computers in the process of subsequent processing of information,

Formula of invention

Claims (1)

1. An device for associative encoding and volumetric compression of information containing a memory block, the first and second outputs of which are connected to the first inputs of the first and second code selectors, respectively, the first groups of outputs of which are connected to the inputs of the same encoders, the third encoder, counter, trigger, element And, the second output of the first code selector is connected to the first input of the first pulse generator; the third output of the memory unit is connected to the first input of the control unit, the second to fourth inputs of which are input According to the start of the start, the end of the cycle and the reset of the device, the first and second outputs of the control unit are of the same name as the control outputs of the device, so that, in order to increase the speed of the device, it has a third code selector 5, a second pulse generator, a code conversion unit, a key block and the first and second delay elements, the first encoder outputs are connected to the first inputs of the code conversion unit, the first inputs of the memory block are connected to the first outputs of the second selector and, a second output is connected to the first inputs of the second pulse shaper owls and element And, the outputs of the second encryption-40 input flea keys; the sixth controller is connected to the second inputs of the code conversion unit and the memory unit, the third outputs of the first code selector are connected to the first inputs of the third encoder, the outputs of which are connected to the third inputs of the conversion unit, codes and the first inputs of the third code selector, the fourth fourth output of the first selector code is connected to the second inputs of the third encoder and the code selector, the first output of which is connected to the second input of the first code selector, the first and second outputs of the first pulse generator are connected to the second to the rum and third inputs of the second code selector, the third output of which and the fifth output of the first code selector are connected to the third and fourth inputs ten 15 A 148410 the third code selector, the second and third outputs of which are connected to the fourth and fifth inputs of the block. e-. generating codes, the first - third outputs of which are connected to the same information inputs of the key block, the third output of the control unit is connected to the fifth input of the third code selector, the third input of the first code selector and the second input of the first pulse generator, the third output of which is connected to the second the input of the second pulse generator, the output of which is connected to the input of the first delay element and the first inputs of the trigger and counter, the outputs of which are connected to the third inputs of the memory unit and a quarter of 2Q forms atsionnm input key unit, the fourth WELLING control unit is connected to the fourth inputs of the first and second code selectors, the third input of the second form controller and the second input of the counter output of the first delay element directly and through the second delay element are connected respectively to the fourth memory input and the second input of the element And, the output of which is connected to the sixth input of the third code selector, the fourth and fifth outputs of which are connected to the fifth and sixth inputs of the control unit whose fifth output is connected to the seventh in the course of the third code selector, the sixth input of the code conversion unit and the second inputs of the trigger, the output of which is connected to the first one: information 25 thirty 35 my outputs of the control unit are connected to the nepBbLM and the second control inputs of the key block, the outputs of which, tc information -5 and outputs c; the devices, the fifth inputs of the memory block are the information inputs of the device, the seventh input of the control block is the clock input of the device 2, The device according to claim 1, that is, that the memory block contains a memory module, the first and second groups of keys, the decoder, switch the first single vibrator and the OR element connected in series, the second single vibrator and the delay element, output, which is connected to the control input of the first group of cells, outputs p; five u, iF) .i K i ;; piii.iM. i (-multiple module, jiRiMif laPT Opa connectors are connected to perocular switches and second I and pyiTiu.i keys, the outputs of which and the output of the first mono-mountain are connected to the second and third inputs of the storage module, information inputs of the first group the key inputs of the OR element, the inputs of the decoder and the input of the first one-shot are the first, third and fourth inputs of the block respectively, the fourth inputs of the storage module are the fifth inputs of the block, the first, second and second outputs of the storage module and the output of the switch First, second and third block outputs, respectively 3. The device according to 11.1, that is, that the first code selector contains the first - fifth groups of elements AND, the first and second groups of elements OR, the group of elements NOT, the resistor, the source constant voltage and triggers, the S-codes of which are the first inputs of the selector, the inverse output of the first trigger connected to the first input of the first element And the second group, the second input of which is combined with the first input of the first element And the first group and is the second input of the selector , the output of the first element And the first group is zero th output of the first group of outputs of the selector, inverse output of the i-ro trigger (a 2, n, n + 1 width of the first inputs of the selector) is connected to the first inputs of the i-ro element of the second group and (il) -ro element And the fifth group, the inverse output of the (n + 1) th trigger is connected to the first input of the nth element and the fifth group, the output (i -) - ro of the element And the second group is connected to the second input of the i-To element PI of the second group and the first input of the i-ro element And the first group, the output of the n-th element And the second group is connected to the first input of the (n + 1) -th element And the first group The two outputs of the second - (n +) - th element of the first group are connected to the first inputs of the first - nth elements OR of the second group, respectively, the first - nth outputs of the third group of outputs, the first inputs of the AND elements of the third group are combined and are the third input, the selector, the output, and the elements of the third 15 25 20 40 thirty 35 45 0 five / 48/41 2 its groups are connected to the first inlays of the same-named elements OR first) groups, the second inputs of which are combined and are the fourth input of the selector, the outputs of the IPI elements of the first group are connected to the R-inputs of the same trigger, the outputs of the HE elements of the group are connected through a resistor to the output of the constant source voltage and are the second output of the selector, the outputs of the elements OR of the second group are connected to the first inputs of the same elements of the fourth group, the output (il) -ro of the element AND the fourth group is connected to the second inputs of the 1st e The elements of the third and fifth groups and the i-ro element OR of the second group, the elements of And the fifth group are the third outputs of the selector, the output of the n-th element of the fourth group is connected to the second input of the (n + 1) -th element of the third group and is the fourth output of the selector, the direct output of the first trigger is connected to the input of the first element of the NOT group, the second inputs of the first elements of the first, third and fifth. groups and the first element OR of the second group and is the fifth output of the selector, the direct outputs of the second - (n + 1) -th triggers are connected to the inputs of the same name NOT the group and the second inputs of the same name AND the first group and the first - nth elements And the fourth group. 4, The device according to claim 11, which means that the second code selector contains the first - fourth groups of elements AND, the group of elements OR, the group of elements NOT, the first and second resistors, the source of a constant voltage switches and triggers, the S inputs of which are the first inputs of the selector, the inverse output j of the trigger (j 1, n, n + 1 is the width of the first inputs of the selector) connected to the first input of the j-ro element of the second group, the outputs of the first - (nl) -ro elements And the second group are connected to the first inputs of the second - the n-th elements And the first and second inputs of the second - n-th element And the second group, the output of the n-th element And the second group is connected to the first input (n + 1) -th element And the first group, the first input of the first element And the first group and the second input of the first element And the second group are combined and appear second inlet home cejieK i opa, direct my.chod gtervogch) 1-rigger connected to the input iiepnofo e.Pymen Ga FIE group n the second flow of the first element And the first group, direct output (j +) - ro trigger soi One with the input (j + l) -ro of the element NOT of the group, the second input of the (i + l) -ro of the E-Meirra T of the first group and the first input of the j-of the element AND of the fourth group, the first inputs of the elements of AND of the third. The outputs of the elements of the third group are connected to the first inputs of the elements of the OR group, the second inputs of which are combined and are the fourth input of the selector , the outputs of the elements OR of the group are connected to the R inputs of the same trigger, the output of the j-ro element AND of the first group is connected to the second inputs jx of the elements AND of the third and fourth groups and is the (jl) -M output of the first group of outputs of the selector, output (n-1 ) -th element AND of the first group is connected to the second input of the (n + 1) -th element AND of the third group and is the nth output of the first group of outputs of the selector; the outputs of the elements of the NOT group are combined with the first terminal of the first resistor and are the second the output of the selector, the outputs of the elements And the fourth group through in The second resistor is connected to the second output of the first resistor and the output of the DC voltage source and is the third output of the selector 5, The device according to claim 1, which includes the third code selector one-shot, first-fourth delayed pulse shapers, positive differential extractor, trigger, NOT element, first-fourth AND elements, first and second OR elements, inputs of the first OR element, are the first inputs of the selector, the output of the first OR element is connected to the positive selector input differential output, the output of which is connected to the first inputs of the second and fourth elements, the first and second inputs of the first element are the second and third inputs of the selector, the output of the first element I is connected to the first input of the trigger, the input of the element P is NOT combined with the second input of the third element AND is the fourth move of the selector; the element output connects to the second input of the second:) Lemma 1 a AND, output to torogs) connected to the i-pti i-btM-o Formed.p delayed 1H1 li iiiy. The nira and the control input of the single-slot UG.GUI, information whose input is HHJia is the fifth input of the selector, the first input of the second element I.PI and the second input of the trigger are the sixth and seventh inputs of the selector, the first output of the trigger is connected with the second input of the fourth element AND, the output of which is connected to the second input of the second element OR, the output of the third element AND is connected to the input of the fourth shaper of the delayed 1-pulse, the output of the one-oscillator. is the first output of the selector, the second output of the trigger is connected to the third inputs of the second and third elements, the input of the first delayed pulse shaper is the second output of the selector, the output of the first delayed pulse shaper is connected to the input the second ground pulse generator is the third output of the selector, the output of the second one is. the body of the delayed pulse is the fourth output of the selector, the outputs The third and fourth delayed pulse formers are connected to the third and fourth inputs of the second SHS element, the output of which is the fifth output of the selector „ 6, The device according to p., About tl and -. that the code conversion block contains the first and second registers, the first to fourth adders, the first and second groups And elements, And element and group of elements of RSHI, the first inputs of which are respectively combined with the first inputs of the first adder and are the first inputs of the block, the first inputs The second and second inputs of the first adders are auto-secondary and pbnvfH are the third inputs of the block, the outputs of the first adder are connected to the first inputs of the third and fourth adders and the first group of elements AND whose outputs are connected to information inputs of the first register whose outputs are connected to the second inputs of the third adder whose outputs are the first outputs of the block; the outputs of the group of elements OR are connected to the second inputs of the fourth adder whose overflow output connected to the first input ele13U And the second input of which is the fourth input of the block, the outputs of the rands of the fourth adder are connected to the first inputs of the second group of elements AND and are the second outputs of the block, the outputs of the elements AND of the second group are connected to the information inputs of the second register, the outputs of which are connected to the second the inputs rpyn of the elements OR, the second inputs of the groups of elements AND and the control inputs of the registers are respectively combined and are the fifth and sixth inputs of the block, the output of the element AND is connected to the second input of the second adder, the outputs These are the third outputs of the block. 7. The device according to claim 1, about tl and - that the control unit contains the first - third triggers, the first and second shapers of the delayed pulse, the first and second elements And, the first and second elements OR, the first input of the first ele - OR is the first input of the block, the second input of the first element a OR is combined with the S input of the first trigger and is the second input of the block, the R input of the first trigger is the first input of the block, the output of the first OR input is connected to the first inputJ7 484 „ the house of the first element AND, the output of which is connected to the S-input of the second flip-flop whose R-input is combined with the input of the first delayed pulse shaper and is the fourth input of the block, the first input of the second OR element is the fifth input of the block, the S-input of the third trigger is The sixth block input, the forward output of the third flip-flop is connected to the first input of the second element I, the second input of which is the seventh input of the block, the forward and inverse outputs of the second flip-flop are the first and second control outputs of the block, the output of the second The OR element is connected to the R input of the third trigger and is the third output of the block, the output of the first delay pulse generator is the fourth output of the block, the output of the second delay pulse generator is connected to the second input of the second OR element, and the fifth output of the block, the output of the second element I is connected to the input of the second delay pulse generator and is the sixth output of the block, the direct output of the first trigger is connected to the second input of the first element AND, and is the seventh output of the block 26 3ff f L 40 V fie.2 ,five - 6i B / 7 1, W in „ .} FIG. Fi2.6 ff9 118 LI t /// FIG. 7 FIG. eight 5Z Fig.Z